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AM3357 L3 access speed

Huang Derek
Intellectual 360 points
Other Parts Discussed in Thread: AM3357

Hi,

    I have a question about the access cycle time of L3.

    When MCU reads 16bits from L3,

    how many cycle times does it cost?

  • 0
    TI__Guru**** 393215 points
    Hi Huang,
     
    The A8 core has both 128-bit and 64-bit access to the L3, and the L3 is clocked at 200MHz.
     
    Best Regards
    Biser
  • 0 in reply to Biser Gatchev-XID
    Intellectual 360 points

    Hi Biser,

          Thank you for your response.

         I know one cycle time of L3 is 5 ns.

        And I would like to know when MCU accesses 128 bits from L3,

        how many cycle times does it cost?

  • 0 in reply to Huang Derek
    TI__Guru**** 393215 points
    Hi Huang,
     
    You can check section 5 in the DM814X datasheet, and more specifically Figure 5-1 and Table 5-1. I did mention the 128-bit port, but this is only connected to the DDR module. The table lists the possible connections over the L3. As you can see it also depends on the ARM clock frequency (which is typically higher than L3 clock frequency), the frequency at which the slave is running, whether it's connected on the 200MHz L3 or the 100MHz L3, and bit-width of the connection. A lot of variables to take into consideration, I don't think there's a single universal answer to your question. However it can be safely assumed that the L3 is the bottleneck.
     
    Best Regards
    Biser
  • 0 in reply to Biser Gatchev-XID
    TI__Guru**** 393215 points

    Sorry Huang, I mixed up forum threads. I was talking about the DM814X in the post above, but things are pretty much the same. Here it's Table 10-1 and Figure 10-1 in the AM335X TRM, the rest is valid for this processor also.

    BR
    Biser
  • 0 in reply to Biser Gatchev-XID
    Intellectual 360 points

    Hi Biser,

         There is On-Chip Memory(64 KB) with AM3357.

       And  I think I can use this memory as the system data storage,

       but I would like to know when MCU accesses 512 bytes from On-Chip Memory,

       how many clock cycles does it cost?

  • 0 in reply to Huang Derek
    TI__Guru**** 393215 points
    This is the OCMC RAM, described in section 7.2 of the TRM. It's maximum frequency is 200MHz, connected to the fast L3 (also 200MHz), and 32 or 64-bit width. So ideally 512 bytes will transfer in 512 / 8 = 64 cycles + up to 12 cycles initial latency = 76 cycles @ 200MHz = 380ns. However all this is supposing that there is no bus contention on the L3 at transfer time.
     
    Best Regards
    Biser
  • 0 in reply to Biser Gatchev-XID
    TI__Intellectual 1835 points

    The L3 read access incurs latency (as seen by ARM core) for first data of approximately 21 cycles of L3 clock at 200MHz and CPU clock at 600MHz.

    Thanks.

  • 0 in reply to Maneesh
    Prodigy 40 points

    Maneesh said:

    The L3 read access incurs latency (as seen by ARM core) for first data of approximately 21 cycles of L3 clock at 200MHz and CPU clock at 600MHz.

     

    Hi Maneesh,

    Can you tell me, where can I find document about L3 interconnect read access incurs latency ( as you said : "as seen by ARM core" ) ?

    Thanks!