OMAP4460 absolute address access

Petrov,

One possible suggestion would be to look at the x-loader code.  I assume that ultimately you will be using a Linux or Android software release on OMAP4?  In that case, you will ultimately need to modify the x-loader for your platform anyway.

You can see in the release notes, for the 4AI.1.7 release for example, how to download and build the x-loader code: http://www.omappedia.com/wiki/4AI.1.7_OMAP4_Icecream_Sandwich_Release_Notes  The x-loader contains the pin muxing setup.  For example, here is the pin muxing in the x-loader for the Blaze Tablet: http://git.omapzoom.org/?p=repo/x-loader.git;a=blob;f=board/omap44XXtablet/omap44XXtablet.c;h=0cc34978fe49a58b428bde87f304782fdc185fdb;hb=omap4_dev  It sets all of the pin muxing, including input/output and pull type for GPIOs.  

The pin muxing is basically the first step of the x-loader, so you could consider disabling the other functionality in the x-loader (DDR settings, serial port settings, etc) temporarily for your needs as a test program.  If you need help understanding the x-loader code flow in order to do this, let me know.  Alternatively, you could look at the GPIO pin mux setting done in the x-loader as an example to pull into your own stand-alone test program.

Regards,
Gina 

Hi Petrov,

Here would be the programming steps for setting GPIO-64 as an output a wiggling it ...

1. Configure the appropriate pad-mux register for the pad to map the GPIO to the pad.

For GPIO-64 this would be register CONTROL_CORE_PAD0_GPIO63_PAD1_GPIO64 (found in section 18.6 of the 4460 TRM, just search for "gpio_64") with physical address 0x4A10009C. We need to configure the muxmode field to 0x3 to map the GPIO to the pad.

__raw_writew(0x3, 0x4a10009c); // 16-bit write

2. Enable the GPIO module. For OMAP4 devices there are 192 GPIOs and each GPIO module manages 32. For GPIO-64, it is the first GPIO of the GPIO3 module (remember GPIOs are numbered from 0 to 191). To enable the GPIO3 module we need to set the modulemode field in the register CM_L4PER_GPIO3_CLKCTRL (found in section 3.11 of the 4460 TRM) with physical address 0x4A009468 to 0x1.

__raw_writel(0x1, 0x4a009468); // 32-bit write

3. Set the GPIO as an output by setting the appropriate bit in the GPIO_OE register. GPIO-64 is in GPIO3 module and it would be the first GPIO so we write 0x1 to the GPIO_OE for GPIO3.

__raw_writel(0x1, 0x48057134); // 32-bit write

4. Toggle the GPIO by setting/clearing the appropriate bit in the GPIO_DATAOUT register. GPIO-64 is in GPIO3 module and it would be the first GPIO so we write 0x1 to the GPIO_DATAOUT for GPIO3.

u32 val;

val = __raw_readl(0x4805713c);
__raw_writel((val | 0x1), 0x4805713c); // toggle high
__raw_writel((val & ~0x1), 0x4805713c); // toggle low

One important caveat! Some pads on the device have separate power rail to the main 1.8V (see the "Ball Characteristics" section in the data manual) and for these pads you may need to make sure the power rail is on. Also some pads such as the MMC are dual-voltage and GPIOs mapped to these pads require some extra configuration. Here is a footnote from the TRM on the dual-voltage pads ...

"This pad is built on an I/O cell of the extended-drain type, which can be configured to operate within the 1.8-V (standard) or 3.0-V (high) I/O power supply voltage range. A PBIAS cell, which acts as a level shifter, is connected to the extended-drain I/O cell of this pad to appropriately bias its voltage according to the externally applied I/O power supply voltage.
To ensure I/O safe operation at 1.8 V or 3.0 V and desired signal performance, the extended-drain I/O cell and its corresponding PBIAS cell must be appropriately configured by software prior to signal selection on the pad, regardless of the signal multiplexing mode. For more details on extended-drain I/O cell and PBIAS cell descriptions and settings,see Section 18.4.9, Extended-Drain I/O and PBIAS Cell, and Section 18.5.1.2.2, Extended-Drain I/Os and PBIAS Cells Programming Guide."

Cheers

Jon