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How to use the EtherCAT PDI Digital I/O interface on the AM335x PRUSS

Is the EtherCAT PDI Digital I/O interface supported by the AM335x PRUSS?

I guess that it is not supported because the latest ISDK does not support "PDI side register permissions".

http://processors.wiki.ti.com/index.php/AM335x_SYSBIOS_Industrial_SDK_01.00.00.05_Release_Notes#What_Is_Not_Supported

If it is not supported, is there the plan that it is supported in future?

Best regards,

Daisuke

 

  • Hi,

    No - TI slave support PDI interface type of onchip bus as EtherCAT is integrated with host processor. We do have a h/w block within PRU-ICSS to support digital I/O - only 8-bit digital input or output is mapped to AM335x pinout and there is no plan to support this in the firmware at this moment.

    Digital I/O PDI is mainly meant for simple slaves without any host processor and stack, but TI EtherCAT slave belongs to complex slave category. Please let us know more on the usecase so that we can look into the feasibility.

    PDI register side permissions is not related to Digital I/O PDI, Basically it means register permissions to various EtherCAT registers are not honored in current implementation from PDI side - A8 host stack. From EtherCAT master side (accesses over network) - it is very well protected and WKC increments happen according to access permissions. This is the most common usecase we can foresee as PDI side access limited to stack and A8 application alone.

  • Hi Pratheesh,

    Thank you for your reply.

    Sorry. I did not know the purpose of the PDI interface on the EtherCAT slave controller.
    I could find that it connect to the host controller such as MCU or FPGA.
    For AM335x, the controller means A8 host stack.
    Therefore, I could understand that PDI interface was not usually used for AM335x.

    Our customer wants to use the prepared pin for Digital I/O.
    I ask them what kind of purpose they want to use those pins in.

    Best regards,

    Daisuke

     

  • Hi Pratheesh,

    Our customer wants to use the prepared pin for Digital I/O as GPIO.
    Those pins can be driven in sync with EtherCAT system time.

    It is not decided what kind of purpose those pins are used in at this moment and it is only reserved for future system expansion.

    Best regards,

    Daisuke