Is EDMA3 support Memory block transfer, when cache is enabled?

Hi,

After disabling the Cache, whether block transfer (using EDMA) is working for you?

Have you tried with examples & sample applications given in Starterware, DSP/BIOS programs and etc.

What is the output of this?

-Thanks,

Balaji N

Hi

We tried our code without enabling cache in DSP. And it worked perfectly ; we also tested the memcpy function in C lib. I need to know whether EDMA or IDMA is supported in EDMA block transfer.  

I found nothing related to DDR since EDMA  block transfer is not working with Shared RAM also. We refereed starter ware code from TI while writing the EDMA driver code. Is there any configuration in EDMA which is related with cache?

Thanks

Hi Shino,

When you say block transfer is not working, does it mean there is no transfer or transfer has happened with invalid data?

Have you taken care of coherency between DSP and EDMA w.r.t. shared RAM? (like cache flush etc)

Regards

Radhesh

You may want to refer to Section 2.4 in the following doc, if I have understood your problem correctly.

http://www.ti.com/lit/ug/sprug82a/sprug82a.pdf

Regards

Radhesh

Thanks for the reply,

In my case the buffer location is not showing any data. We cleared both source and dest buffers prior to copying. I also like to know that is there any options to be handled inside EDAM3 peripheral driver to accommodate  cache functionality. 

thank u.

Hi Shino,

If there is any cache issue, then atleast transfer should be complete and you may see invalid data. But in your case, there does not seem to be transfer being happening. Am I right? Can you let me know the way you are configuring the cache ( I mean how much size are you configuring as cache and remaining as RAM in L2)? Are you making sure that you are not configuring addresses for EDMA in L2 from cache region?

Regards

Radheh