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Bandwidth Management Priority in the C674x megamodule for the cache controller

Daisuke Maeda
Guru 20205 points

For the User defined cache coherency operations, it is Fixed priorities.

TMS320C674x DSP Megamodule Reference Guide (Rev. A)
http://www.ti.com/lit/ug/sprufk5a/sprufk5a.pdf
Table 6-1. Priority Declaration Methods

What are levels of its Fixed priorities?

For the User undefined cache operations (which are initiated by the cache controller), what are Priority Levels?

Best regards,

Daisuke

 

  • 0
    Guru 20205 points

    Requestors Managed by Bandwidth Management are below.

    TMS320C674x DSP Megamodule Reference Guide (Rev. A)
    http://www.ti.com/lit/ug/sprufk5a/sprufk5a.pdf
    6.1.3 Requestors Managed by Bandwidth Management

    Do the CPU-initiated transfers include the cache controller-initiated transfers?
    I think that the cache controller-initiated transfers are initiated by the CPU.

    I want to know the details of Bandwidth Management Operations when the cache controller-initiated transfers and EDMA-initiated transfers conflict.

    Best regards,

    Daisuke