Hello TI community!
We have a custom am3517 board.
On some boards we have been experiencing random kernel crashes (linux 2.6.37 from arago git).
Further investigation has shown that this might be due to DDR2 issues. Running memtester from linux on faulty boards confirms
that some memory operations fail (especially the bit-flip test). We are using 2x128MB Winbond W971GG6JB chips where one chip uses the lower 16 bits of the 32bit address/data and the other chip the high 16 bits (one CS used).
We have found that setting EMIF4_CFG_DDR2_DDQS=0 (single ended datastrobe) makes these boards pass all memory tests.
It is also impossible to start u-boot when full drive strength (EMIF4_CFG_SDR_DRV=0 in x-loader) is used.
We are pretty sure that the timing registers EMIF4_TIM(1-3) are OK. We have checked these with the spreadsheet tool, values from datasheet
gives even narrower values than what we are currently using in x-loader.
One discrepancy on our board is that we are using a 3.3V input to the 26Mhz core clock (SYS XTALIN) and this should be 1.8V according to updated datasheets.
ANY thoughts on why we are getting these symptoms would greatly be appreciated!
- Why does single ended DQS work when differential should be better?
- Could this be a timing problem nonetheless?
- What could cause 100% drive-strength NOT to work when 60% works? Feels like it should be the other way around with DDR2?
- Could this be a problem with supply voltage to RAM?
- Could this be a symptom of 3.3V core clock?
We are hesitant to run our DDR2 with single ended DQS and on reduced drive-strength as we are unsure how this will affect long time reliability.
Best regards,
Anton Olofsson