We are working on OMAP L138. We are trying to do an EDMA from KERNEL buffer to FPGA which is interfaced at EMIF.The FPGA is an 16bit[DATA ] interface.
The following are the behavior on which my doubts are based. :-
a) If my ACNT=32 ,BCNT is 1, CCNT=1,SRC_B_INDX=0, DEST_B_INDX=0, SRC_C_INDX=0, DEST_C_INDX=0.
ON EMIF side i am getting ONE ADDRESS VALUE on ADDRESS BUS.....ADRR=0
a) If my ACNT=33 ,BCNT is 1, CCNT=1,SRC_B_INDX=0, DEST_B_INDX=0, SRC_C_INDX=0, DEST_C_INDX=0.
ON EMIF side i am getting TWO ADDRESS VALUE on ADDRESS BUS.....ADRR=0 for 1st 32 byte & ADRR=1 for 2nd 32 Byte
c) a) If my ACNT=64 ,BCNT is 1, CCNT=1,SRC_B_INDX=0, DEST_B_INDX=0, SRC_C_INDX=0, DEST_C_INDX=0.
ON EMIF side i am getting TWO ADDRESS VALUE on ADDRESS BUS.....ADRR=0 for 1st 32 byte & ADRR=1 for 2nd 32 Byte
d) a) If my ACNT=66 ,BCNT is 1, CCNT=1,SRC_B_INDX=0, DEST_B_INDX=0, SRC_C_INDX=0, DEST_C_INDX=0.
ON EMIF side i am getting TWO ADDRESS VALUE on ADDRESS BUS.....ADRR=0 for 1st 32 byte & ADRR=1 for 2nd 32 Byte
ADRR=2 for 3rd 32 byte.
Can you please help me understand why there is change in address bus value obtained from EMIF even though i am doing an EDMA transfer of 32 / 33/64/66 in ASYNC mode .
As per my understanding i should get only 1 ADDR value even from EMIF interface as i am doing an DIRECT EDMA in ASYNC Mode.
The following is my code snip:-
ret = edma_alloc_channel(EDMA_CHANNEL_ANY , callback1 , NULL, dma_queue);
if ( ret < 0)
{
pr_info("The DMA DRIVER failed to get the channel ...\n");
return(ret);
}
dma_chan = ret ; // dma_chan now has the channel number being allocated
printk("CONFIGURING edma ...the source & destination...\n");
//----------------- Now setting the SRC & DEST addres ....
edma_set_src( dma_chan , (unsigned long) dmasrc , INCR ,W8BIT);
edma_set_dest( dma_chan , ( EMIF_CHIP5_BASE + (BRAM_ADDR) ) ,INCR,W8BIT);
edma_set_src_index(dma_chan , SRCBINDX , SRCCINDX) ;
edma_set_dest_index(dma_chan,DESTBIND
Thank You,
Ashish