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about PCIe in ACK_DISABLE mode

wk kim
Prodigy 10 points

HI

I want to check the throughput difference between DLLP ACK_ENABLE and ACK_DISABLE mode.

I ve got the result at ACK_ENABLE mode, that is similar wiith mentioned throughput in sprabk8.pdf document

But when I try to do same thing at ACK_DISABLE mode, there is a problem.

When RC writes something to EP, there is nothing in EP's destination memory.

I ve changed to laneSkew.ackDisable =  1 in PCIe register.

 

1. Is there something more to change for ackDisable mode?

2. If I change ackFreq in Ack Frequency Register (ACK_FREQ) Field to 0, is it same with ackDisable mode?

 

I have two 6678 EVMs, one for RC, the other for EP and they are connected with a bridge board.

 

  • 0
    TI__Genius 12065 points

    Kim,

    I think the ACK/NAK DLLP and flow control DLLP are required to maintain the correct TLP transactions over the PCIe link.

    The default setup in C66x PCIe module is already minimal flow control and minimal ACK/NAK device latency. 

    The default ACK_FREQ field setup provides the capability to accumulate up to 255 ACKs before issuing an ACK. This provides the minimal overhead introduced by ACK DLLP.

    The ACK_DISABLE field may be used for debug purpose only. Please leave it as the default setting.

    We will update the PCIe use case application note (sprabk8) later to specify it.  Thanks.