AM1808: System-Level ESD Immunity

Hi Indejit

The key workaround requirement is to have an input clock with a rise/fall time of less than 5 ns. The reason we put a 3.3V ext osc solution with voltage divider ckt was because it is our understanding that 1.2V ext osc are very hard to find. If you are able to get something more cost optimal that provides the recommended rise/fall time , it would work.

Power draw can be an area of concern with this ckt, however if you are using the deep sleep feature of the device, it is plausible to implement discrete solution to shut off the ext osc when in deepsleep mode etc.

Hope this helps.
Regards

Mukul

I would appreciate an answer to my question on if ESD anywhere on the board will cause this issue, or just on or near the oscillator.  Has any testing been done on this, or has it been proven that ESD strikes on I/O lines will cause the problem?

Most CMOS outputs are rated at 6 to 8mA output current.  12.5mA is well above this limit.  Has the circuit been tested?  Was the oscillator's output able to keep the output voltage at 3.3V?

New question:  can the signal on OSCIN track CVDD, or does it have to be a constant 1.2V?

Inderjit

Inderjit Bains said:

I would appreciate an answer to my question on if ESD anywhere on the board will cause this issue, or just on or near the oscillator.

The region around the OSCIN/CLKIN is most sensitive, but overall sensitivity will depend on the board design, we have seen susceptibility in other customer designs where the board was susceptible from other directions as well.

Inderjit Bains said:

Has any testing been done on this, or has it been proven that ESD strikes on I/O lines will cause the problem?

Most CMOS outputs are rated at 6 to 8mA output current.  12.5mA is well above this limit.  Has the circuit been tested?  Was the oscillator's output able to keep the output voltage at 3.3V?

If you are asking if the solution in the usage note has been tested etc, yes, it is now in production in several designs.  Previous versions of the same designs had a crystal and would fail system esd tests (direct and indirect) around ~3-5KV

Inderjit Bains said:

New question:  can the signal on OSCIN track CVDD, or does it have to be a constant 1.2V?

Not sure I understand this question, you would want a 1.2V square clock input.

Regards

Mukul

OSCIN's threshold levels are 0.8*CVDD for high-level and 0.2*CVDD for low-level (table 5.2, AM1808 datasheet).  Will a buffer with its power supply connected to CVDD work?  CVDD will vary from 1.0V to 1.3V.

Inderjit

No, a simple buffer might not work. This was tried and did not improve the results. So if you plan to try this as a solution, I would recommend stringent system ESD testing on your board, prior to mass production.

Keep in mind,  the best way to test some of these workarounds would be to actualy do a layout to incorporate the components etc, blue wiring existing crystal based designs, might not reflect true results due to possibly amplification of noise by the buffer etc.

Why didn't the buffer work?  Was it tried with CVDD as the power source, or a fixed 1.2V regulator?  A buffer should be better than a resistive divider - faster rise and fall times.

Ordinary buffers do not have hysterisis.

The noise margin on this input is a function the the slew rate of the input signal and the input buffer hysteresis.

 I don't recall all the details. As I mentioned earlier, if you plan to try this solution, or anything outside the recommendations in the usage note, you will need to try this out in your system.

Just to be clear - I'm talking about using a buffer in place of the resistive divider.  The output from the oscillator should be a square wave, which would be stepped down to 1.2V by the buffer.  I'm not sure why hysteresis would be required, as the rise and fall times from the oscillator should be fast.

Ok,  thanks for the clarification. I digged through the test suites, and I see that a buffer was tried but did not work *however* seems like the buffer that was used had a 20 ns/V rise/fall time rate.

FYI for the current draw issue, I believe one customer had tried a a capacitor divider ckt with series resistor and it seemed to work too.

So to recap/resummarize what I said earlier, as long as you can get the rise/fall time below 5nsec, provide a CLKIN that is within the datasheet recommended spec,  test out the prototype prior to mass production (if you are trying implementations outside of what is put in the usage note) , any implementation should be fine.

Regards

Mukul

One last question:  how is deep sleep handled with an external oscillator?  There doesn't seem to be an automatic way of shutting the oscillator down during deep sleep.  Using a GPIO won't work - no software will be running when the wakeup event occurs.

Second last question :) is OSCIN referenced to CVDD?  If so, is it safe to apply a 1.3V clock to it?  What happens if CVDD is at 1.0V (core voltage scaling)?  Are there any power sequencing issues with a clock on OSCIN with CVDD at 0V?

Hi

I checked with design on this

Inderjit Bains said:

If so, is it safe to apply a 1.3V clock to it? 

The OSCIN buffer is powered by CVDD.

Inderjit Bains said:

is OSCIN referenced to CVDD? 

1.3V clock is OK.

Inderjit Bains said:

What happens if CVDD is at 1.0V (core voltage scaling)?  Are there any power sequencing issues with a clock on OSCIN with CVDD at 0V?

I assume the question is, what if input is 1.3V and CVDD=1.0V. This should be OK. There is no specific power sequencing for OSCIN. If CVDD=0V and a clock is driven in at 1.3V, the input will get clamped and the current will be high until CVDD is powered up. Should minimize supply ramp to prevent long term of high current.

Yes, I think i over simplified the discussion on deep sleep + ext osc. If you want to power down the ext osc, when the device is in deep sleep , the assumption is that you are using the DEEPSLEEP pin and can route that as enable/disable for ext osc too.

A simple delay buffer can be added to the DEEPSLEEP# signal in order to keep the oscillator enabled for the required ~100 cycles after the DEEPSLEEP# signal is asserted. If the I/O voltage levels for the oscillator standby pin and the AM1806 DEEPSLEEP# pin differ, additional voltage translation will be required.

It may be a bit more complex than that:  if the DEEPSLEEP# signal is indeterminate at power-up, just a delay buffer won't work:  the oscillator may not start.

But thanks for all the detailed answers - very much appreciated!

If the input to OSCIN is a 24MHz, 1.3V square wave with 3.5ns rise/fall times and a 50% duty cycle, what is the worst-case duty cycle for a 24MHz, 1.8V output at CLKOUT (pin T18)?  PLLC0 OSCSEL[OCSRC]=0x14, PLLC0 OSCDIV [RATIO] = 0 (divide by 1).