We’re using TI 'C67xx DSPs now and currently looking at two ways of handling a data analysis problem:
- Sample and hold in analog domain, digitize peak and process in DSP (10 Msamples/sec)
- Digitize analog signal and peak fit in the DSP (250Msamples/sec)
In method #1 I envision using the Universal Parallel Port (uPP) on a C674x DSP to clock data out of our FIFOs. We have 2x14-bits of data, so with the 16-bit uPP bus, we’ll actually have 20 Msamples that we need to clock in, but it looks like the uPP will clock up to 75MHz and clocks valid data on every clock edge so that should easily meet our needs.
In method #2 we either need a very fast parallel interface into the DSP (as well as a fast CPU) or we will need to do most of our processing in an FPGA. I’ve looked around the TI website and it looks like the two highest clock rate DSPs are the C6671 at 1.25GHz (and its multi-core siblings) or the C6457 at 1.2GHz. However I don’t see a fast parallel port on the C6671 and the EMIFA on the C6457 appears to max out at 100MHz.
Are there any DSPs in the TI line that have a 32-bit 250MHz parallel interface to the external world?
Any feedback or input is welcomed and appreciated!
Thanks again!
Paul
