Catching DSP MMU interrupt?

I'm not sure I can help with this one, but are you saying you want a DSP data and/or instruction fetch of location 0x00000000 to result in a bus error?

When you refer to the DSP MMU are you talking about the SCACHE_MMU as described in section 5.4/5.5 of the OMAP4430 TRM?

If so, in order to enable the MMU to generate an interrupt when a page fault occurs, you have to take the SCACHE out of bypass mode by setting bit 1 of the SCACHE_CONFIG register to a 1. Be advised though that when not in bypass mode, every address accessed by the DSP must have a corresponding MMU page descriptor associated with it or an interrupt or bus error will occur.

Alan

Sorry, should have been more specific. I'm referring to the DSP L2 MMU described in Section 20 of the TRM.

I'm not at all familiar with the L2 MMU.

I'm forwarding your question to a few colleagues to see if they can help.

Alan

Edward,

This question actually seems more devie-centric and less about BIOS.  I have moved this thread over to the OMAP4 forum in hopes that it will get a faster response there.

Dave

I haven't went that down in the information to read about how caches are controlled when reading SYSBIOS documentation, but by I found next links

http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/bios/sysbios/6_33_04_39/exports/bios_6_33_04_39/docs/cdoc/index.html

the Cache section for DSP is in:

http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/bios/sysbios/6_33_04_39/exports/bios_6_33_04_39/docs/cdoc/ti/sysbios/family/c64p/Cache.html

http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/bios/sysbios/6_33_04_39/exports/bios_6_33_04_39/docs/cdoc/ti/sysbios/family/c64p/MemoryProtect.html

http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/bios/sysbios/6_33_04_39/exports/bios_6_33_04_39/docs/cdoc/ti/sysbios/family/c64p/Exception.html

The "Details" section for MemoryProtect contains some information that sounds what you are looking for.

and an important link that mentions TLB.

http://processors.wiki.ti.com/index.php/DSP_MMU_Faults

other link, if you follow download link you can find .chm file version

http://processors.wiki.ti.com/index.php/Category:SYSBIOS

Edward,

Is this issue resolved per the information that Manuel sent?

Regards,
Gina 

No. My question was about the DSP's virtual/physical translation MMU described in section 5.3.4 and 20 and of the TRM, NOT the shared cache attribute MMU described in section 5.3.2.5 and referred to by Alan and Manuel.

I was perhaps not as clear as I could have been, since there seems to be a bitof confusion about which MMU I was asking about. To re-state my question, I wanted to be able to detect a TLB miss event in the translation MMU on the DSP and could not determine how to accomplish this. This event did not seem to map clearly to any of the DSP interrupt mappings listed in Table 5-6. Experimentation with a few potential matches (such as a BUSERR interrupt) have produced no useful ability to detect & handle a translation MMU TLB miss on the DSP.

My tentative conclusion based on language in section 20.2 ("DSP MMU and Cortex-M3 MMU error conditions are signaled as interrupts to the system main processor Cortex-A9 MPU.") is that it is not possible to detect or handle the error condition I am interested in on the DSP. I've have proceeded by detecting/handling the TLB miss on the A9, triggered by the DSP MMU interrupt described in Table 17-2.

My solution does NOT address my original question (can this be done on the DSP?), but renders it moot for the time being.

Edward

i am looking into this and will try to see if this is possible or not.

Regards

Mohsen

Comment;

I thought that from previously shared links and the TRM information about what you mention in first post issue could be solved.

My idea was to use the SYSBIOS Cache and MemoryProtect objects to get the Exception that you are looking for, this exception is catch in the exceptions for cache.memoryprotect code. It is needed to indicate the valid memory regions to the cache as indicated in the previous link with an example.

From your last post and HW perspective it seems answer is more complex involving the way to decode the interrupt in the DSP INTC.

I can suggest to ask in the next forum that is for DSP they should be able to provide the answer. From TRM the DSP in OMAP4 is a derivative of TMS320DMC64x+^TM.

C64x Single Core DSP Forum

For what I know the interrupt is catch in DSP side and then if you need it in other processor you need to communicate it using some programming method, a bridge or rpmsg at least for this case or for memory access error in DSP side.

Thanks, much appreciated.