AM1808 DDR2 SDRAM Configuration

Inderjit

1. The page size is calculated as the number of columns in the SDRAM memory times the number of data bits:

PAGESIZE = 2^n * data bus width.

2. Can you please send me the spreadsheet you have? I don't see how 70us tRAX max would overflow the T_RASMAX field. Can you also please send the SDRAM datasheet?

3. You can find the row size info in the SDRAM data sheet.

Thanks
David

1.  Table 14-25 in the TRM, bits 2-0:  for a 16-bit wide SDRAM chip with 10 column address bits, which value is used?  0x2 or 0x3?

2.  http://www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/1Gb_DDR2.pdf.  See Table 11, under Average periodic refresh (industrial).  Use 3.9us for tREFI and 70 for tRAS(MAX) and the calculated T_RASMAX will be 16 (ROUNDDOWN(70/3.9 - 1).  This overflows into bit 31 of SDTIMR2, which should always be 0 according to Table 14-28 in the TRM.

3.  My question again:  there's no place for the row information on the spreadsheet - why is this?  In OMAP-L138/Common/src/device.c,  DEVICE_ExternalMemInit's 6th parameter is SDCR2, but it's always passed as 0x00000000.  How is the row information determined in UBL/SFH?

Inderjit

1. It should be 0x2.

2. I am still trying to get an answer from our designer, I believe you just programmed the max value of 0x1111b.

3. The rwo information is not being used in the timing calculation, I believe this is the reason it is not inclued in the spreadsheet. The value of 0x00000000 corresponds to 9 rwo address bits.

Thanks
David

Inderjit

For question #2, Since tRASmax is a maximum time, i.e., the time programmed in the EMIF register field must be lower than the tRASmax=70us required by the SDRAM. Therefore, for refresh_rate=3.9, if the required tRASmax=16d, you can always program 15d in the register field and still meet the timing.

Thanks

David

#3:  The only place in device.c where SDCR2 is set is within function DEVICE_ExternalMemInit():

// Check if this init is for mDDR
  if (sdcr & DEVICE_SDCR_MSDRAMEN_MASK)
  {
    // If it is, set SDCR2 with PASR and ROWSIZE PARAMS
    EMIF3A->SDCR2     = sdcr2;
  }

As you can see, it is only set if the SDRAM is Mobile DDR.  256 MBit, 512 MBit, and 1GBit DDR2 SDRAM chips (x16) all use 13 row address lines.  256 MBit uses 2 banks and 9 column bits, 512 MBit uses 2 banks and 10 column bits, and 1GBit uses 3 banks and 10 column bits.  A row size of 9 would be for very small capacity DDR2 SDRAM chips.  What is the default size of the DDR2 150MHz SDRAM chip?

Inderjit

The SDRCR2 register is applicable only when the IBANK_POS bit in the SDRAM configuration register (SDCR) is set to 1 for special addressing. This does not impact the normal SDRAM operation. Are you setting the IBANK_POS bit to 1 for special addressing?

Thanks
David

No, I'm not setting IBANK_POS to 1.  Does the SDRAM controller determine the number of row bits, or is this just set in u-boot as the maximum memory size (PHYS_SDRAM_1_SIZE in da850evm.h)?