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GMII PLL clock source

Dennis McLeod
Intellectual 925 points

The user guide (sprugz7b) has the ethernet clock in the PCIE_PLL_CFG1 register, but  other references and figure 9-2 in the same guide say that the clock comes from the SATA PLL. Which is correct for GMII?

Or if anyone has done this work of using the GMII1 interface before, would you mind sharing what registers/modifications were made?

Thank you in advance.

  • 0
    TI__Guru**** 170625 points

    Hi Dennis,

    The GMII ref clock (125MHz) come from SATA. The whole path is: DEVOSC (20MHz) -> PCIe -> SATA -> GMAC switch. You can check the whole picture here:

    sprugz7b, 2.3.6 SERDES and Ethernet Clock Structure

    Also this thread is explaining how to enable the second ethernet port (port1):

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/214043/762567.aspx

    Best Regards,

    Pavel