AVSYNC error . how can i reset m3vpss ?

kisung cho

Hello,

6406.201210020942.pdfI'm using TI8167 , udworks DVRRDK03.00.00.00

I think this error caused by asynchronous CVBS input. How can I solve this problem?

can i detour this problem by m3vpss reset?

[m3vpss ] AVSYNC:WallTime IGNORE Unexpected Discontinuity.PrevTs[9391770]/CurTs[9394072]
[m3vpss ] AVSYNC:WallTime IGNORE Unexpected Discontinuity.PrevTs[9394322]/CurTs[9396658]
[m3vpss ] AVSYNC:WallTime IGNORE Unexpected Discontinuity.PrevTs[9397008]/CurTs[9399294]
[m3vpss ] AVSYNC:WallTime IGNORE Unexpected Discontinuity.PrevTs[9399511]/CurTs[9400352]
[m3vpss ] AVSYNC:WallTime IGNORE Unexpected Discontinuity.PrevTs[9400352]/CurTs[9402080]
[m3vpss ] AVSYNC:WallTime IGNORE Unexpected Discontinuity.PrevTs[9402131]/CurTs[9402281]
[m3vpss ] AVSYNC:WallTime IGNORE Unexpected Discontinuity.PrevTs[9402281]/CurTs[9403041]

over 12 years ago

0 Badri Narayanan over 12 years ago

TI__Guru 59700 points

Can you let me know the value of

/dvr_rdk/mcfw/src_bios6/links_m3vpss/avsync/avsync_m3vpss.h

#define AVSYNC_GET_HW_TIME()

Is it

#define AVSYNC_GET_HW_TIME() (Utils_getCurTimeInMsec())

#define AVSYNC_GET_HW_TIME() Utils_dmTimerGetCurTimeInMsec(SYSTEM_DMTIMER_ID);

If it is

#define AVSYNC_GET_HW_TIME() Utils_dmTimerGetCurTimeInMsec(SYSTEM_DMTIMER_ID);

can you try changing to

#define AVSYNC_GET_HW_TIME() (Utils_getCurTimeInMsec())

and check if you still see the issue

0 kisung cho over 12 years ago in reply to Badri Narayanan

Expert 1460 points

Hellow Narayanan.

my current header file (/dvr_rdk/mcfw/src_bios6/links_m3vpss/avsync/avsync_m3vpss.h) is below.

#define AVSYNC_GET_HW_TIME() (Utils_getCurTimeInMsec())
//#define AVSYNC_GET_HW_TIME() Utils_dmTimerGetCurTimeInMsec(SYSTEM_DMTIMER_ID);

i changed

#define AVSYNC_GET_HW_TIME() Utils_dmTimerGetCurTimeInMsec(SYSTEM_DMTIMER_ID);

and test it . The result is much better, live screen recovered. but sometimes it doesn't recovered within 3 minutes.

and i can see the same avsync error. i attached full log and screenshot.

can you advice me any tuning point in the source code and where modify and test?

Best Regards. CHO8357.201210051031.pdf

0 kisung cho over 12 years ago in reply to kisung cho

Expert 1460 points

i attached my issue video .

0 kisung cho over 12 years ago in reply to kisung cho

Expert 1460 points

Hi Narayanan.

when videoloss channel detected , i can indicate it.

maybe if i indicate videoloss channel to the m3video or force reset m3video,

is it possible make a detour this issue?

0 Badri Narayanan over 12 years ago in reply to kisung cho

TI__Guru 59700 points

Mr.Cho,

I want to provide some background info:

Avsync WallTime discontinuity indicates happens under the following condition:

1. There a 1 ms periodic object.

2. Every 1 ms it reads the H/w timer and checks the elapsed time.

3. If the elapsed time is very different compared to expected elapsed time (1ms) then a warning is printed.

This does not affect Video operation in anyway unless you have CCS connected .If CCS is connected it will result in display getting blanked everytime a print occurs because prints will result in halting the VPSS M3 temporarily . Pls confirm you dont have CCS connected to VPSS M3 in your case.

Now the real problem is it appears there is mismatch between the M3 frequency as configured in uboot and the M3 frequency configured in

/dvr_rdk/mcfw/interfaces/link_api/system_common.h

#define SYSTEM_M3VPSS_FREQ (280*1000*1000)

#define SYSTEM_M3VIDEO_FREQ (280*1000*1000)

#define SYSTEM_DSP_FREQ (800*1000*1000)

Pls check if your uboot sets the same frequency as defined in /dvr_rdk/mcfw/interfaces/link_api/system_common.h. It appears that there is some mismtach here.

0 kisung cho over 12 years ago in reply to Badri Narayanan

Expert 1460 points

Thanks. Narayanan

it's my uboot messages ,and u-boot clocks_ti816x.h code . is there something wrong?

U-Boot 2010.06 (Sep 24 2012 - 14:13:27)

TI8168-GP rev 2.0

ARM clk: 1000MHz
DDR clk: 796MHz
HDVICP clk: 600MHz
L3 Fast clk: 560MHz
HDVPSS clk: 280MHz
Ducati M3 clk: 280MHz

/* Main PLL */
#define MAIN_N 56
#define MAIN_P 0x1
#define MAIN_INTFREQ1 15
#define MAIN_FRACFREQ1 0x1EB851
#define MAIN_MDIV1 0x1
#define MAIN_INTFREQ2 12
#define MAIN_FRACFREQ2 0x189374
#define MAIN_MDIV2 0x1

#define MAIN_INTFREQ3 10
#define MAIN_FRACFREQ3 0x147AE1
#define MAIN_MDIV3 0x2

#define MAIN_INTFREQ4 10
#define MAIN_FRACFREQ4 0xCCCCCC
#define MAIN_MDIV4 0x2
#define MAIN_INTFREQ5 12
#define MAIN_FRACFREQ5 0x189374
#define MAIN_MDIV5 8
#define MAIN_MDIV6 0x3F
#define MAIN_MDIV7 0x4

Regards. CHO

0 Badri Narayanan over 12 years ago in reply to kisung cho

TI__Guru 59700 points

Mr.Cho,

The frequency from uboot looks correct. Anyhow can you compile the attached file and run it from A8 userspace once the kernel is booted up.It will print the PLL settings.When you see this issue are you seeing VIP Reset issue as well or is this unrelated to the VIP reset issue.

Fullscreen 4130.ti816x_pll.c Download

/*
 *  Copyright (c) 2010-2011, Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *  *  Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *
 *  *  Redistributions in binary form must reproduce the above copyright
 *     notice, this list of conditions and the following disclaimer in the
 *     documentation and/or other materials provided with the distribution.
 *
 *  *  Neither the name of Texas Instruments Incorporated nor the names of
 *     its contributors may be used to endorse or promote products derived
 *     from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 *  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 *  PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 *  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 *  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 *  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 *  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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 *  DCMP=TIHomeTracking&HQS=Other+OT+home_d_contact
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 */

#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <string.h>
#include <errno.h>
#include <signal.h>
#include <fcntl.h>
#include <ctype.h>
#include <termios.h>
#include <sys/types.h>
#include <sys/mman.h>

#define DISPLAY_STR(str)  printf (str);
#define DISPLAY_STR2(str, x, y) printf (str, x, y);

#define GEL_TextOut(mstr, sstr, x, y, z) printf ( "CortxA8: Output:    " mstr,z);

#define DISP_ADDRPHY_ADDRVIRT_DATA(x, y, z) printf ("             " "Phy Addr : 0x%0.8x Data : 0x%0.8x\n", x,  z);
#define DISP_ADDRPHY_ADDRVIRT_DATA_BW(x, y, z) printf ("             " "BW Phy Addr : 0x%0.8x Data : 0x%0.8x\n", x,  z);
#define DISP_ADDRPHY_ADDRVIRT_DATA_AW(x, y, z) printf ("             " "AW Phy Addr : 0x%0.8x Data : 0x%0.8x\n", x,  z);

#define MAP_SIZE (1024*1024)
#define MAP_MASK (MAP_SIZE-1)

#define PM_ACTIVE_PWRSTCTRL			0x48180A00
#define PM_DEFAULT_PWRSTCTRL			0x48180B00
#define PM_IVAHD0_PWRSTCTRL			0x48180C00
#define PM_IVAHD1_PWRSTCTRL			0x48180D00
#define PM_IVAHD2_PWRSTCTRL			0x48180E00
#define PM_SGX_PWRSTCTRL			0x48180F00

#define CM_GEM_CLKCTRL				0x48180400
#define CM_HDDSS_CLKCTRL			0x48180404
#define CM_HDMI_CLKCTRL				0x48180408
#define CM_ACTIVE_GEM_CLKCTRL			0x48180420
#define CM_ACTIVE_HDDSS_CLKCTRL			0x48180424
#define CM_ACTIVE_HDMI_CLKCTRL			0x48180428

#define CM_DEFAULT_L3_MED_CLKSTCTRL		0x48180504
#define CM_DEFAULT_L3_FAST_CLKSTCTRL		0x48180508
#define CM_DEFAULT_PCI_CLKSTCTRL		0x48180510
#define CM_DEFAULT_L3_SLOW_CLKSTCTRL		0x48180514
#define CM_DEFAULT_CLKSTCTRL 			0x48180518
#define CM_DEFAULT_EMIF_0_CLKCTRL		0x48180520
#define CM_DEFAULT_EMIF_1_CLKCTRL		0x48180524
#define CM_DEFAULT_DMM_CLKCTRL			0x48180528
#define CM_DEFAULT_FW_CLKCTRL 			0x4818052C
#define CM_DEFAULT_USB_CLKCTRL 			0x48180558
#define CM_DEFAULT_SATA_CLKCTRL 		0x48180560
#define CM_DEFAULT_PCI_CLKCTRL  		0x48180578

#define CM_IVAHD0_CLKCTRL	 		0x48180600
#define CM_IVAHD0_IVAHD_CLKCTRL 		0x48180620
#define CM_IVAHD0_SL2_CLKCTRL	 		0x48180624

#define CM_IVAHD1_CLKCTRL	 		0x48180700
#define CM_IVAHD1_IVAHD_CLKCTRL 		0x48180720
#define CM_IVAHD1_SL2_CLKCTRL	 		0x48180724

#define CM_IVAHD2_CLKCTRL	 		0x48180800
#define CM_IVAHD2_IVAHD_CLKCTRL 		0x48180820
#define CM_IVAHD2_SL2_CLKCTRL	 		0x48180824

#define CM_SGX_CLKSTCTRL			0x48180900
#define CM_SGX_SGX_CLKCTRL	 		0x48180920

#define MAINPLL_CTRL		0x48140400
#define MAINPLL_FREQ1		0x48140408
#define MAINPLL_DIV1		0x4814040C
#define MAINPLL_FREQ2		0x48140410
#define MAINPLL_DIV2		0x48140414
#define MAINPLL_FREQ3		0x48140418
#define MAINPLL_DIV3		0x4814041C
#define MAINPLL_FREQ4		0x48140420
#define MAINPLL_DIV4		0x48140424
#define MAINPLL_FREQ5		0x48140428
#define MAINPLL_DIV5		0x4814042C
#define MAINPLL_DIV6		0x48140434
#define MAINPLL_DIV7		0x4814043C

#define DDRPLL_CTRL		0x48140440
#define DDRPLL_DIV1		0x4814044C
#define DDRPLL_FREQ2		0x48140450
#define DDRPLL_DIV2		0x48140454
#define DDRPLL_FREQ3		0x48140458
#define DDRPLL_DIV3		0x4814045C
#define DDRPLL_FREQ4		0x48140460
#define DDRPLL_DIV4		0x48140464
#define DDRPLL_FREQ5		0x48140468
#define DDRPLL_DIV5		0x4814046C

#define VIDEOPLL_CTRL		0x48140470
#define VIDEOPLL_FREQ1		0x48140478
#define VIDEOPLL_DIV1		0x4814047C
#define VIDEOPLL_FREQ2		0x48140480
#define VIDEOPLL_DIV2		0x48140484
#define VIDEOPLL_FREQ3		0x48140488
#define VIDEOPLL_DIV3		0x4814048C

#define AUDIOPLL_CTRL		0x481404A0
#define AUDIOPLL_FREQ2		0x481404B0
#define AUDIOPLL_DIV2		0x481404B4
#define AUDIOPLL_FREQ3		0x481404B8
#define AUDIOPLL_DIV3		0x481404BC
#define AUDIOPLL_FREQ4		0x481404C0
#define AUDIOPLL_DIV4		0x481404C4
#define AUDIOPLL_FREQ5		0x481404C8
#define AUDIOPLL_DIV5		0x481404CC

#define CM_SYSCLK1_CLKSEL       0x48180300
#define CM_SYSCLK2_CLKSEL       0x48180304
#define CM_SYSCLK3_CLKSEL       0x48180308
#define CM_SYSCLK4_CLKSEL       0x4818030C
#define CM_SYSCLK5_CLKSEL       0x48180310
#define CM_SYSCLK6_CLKSEL       0x48180314
#define CM_SYSCLK7_CLKSEL       0x48180318
#define CM_SYSCLK10_CLKSEL      0x48180324
#define CM_SYSCLK11_CLKSEL      0x4818032C
#define CM_SYSCLK13_CLKSEL      0x48180334
#define CM_SYSCLK15_CLKSEL      0x48180338
#define CM_SYSCLK19_CLKSEL      0x4818034C
#define CM_SYSCLK20_CLKSEL      0x48180350
#define CM_SYSCLK21_CLKSEL      0x48180354
#define CM_SYSCLK22_CLKSEL      0x48180358
#define CM_SYSCLK23_CLKSEL      0x481803B0
#define CM_SYSCLK24_CLKSEL      0x481803B4
#define CM_VPB3_CLKSEL		0x48180340
#define CM_VPC1_CLKSEL		0x48180344
#define CM_VPD1_CLKSEL		0x48180348
#define CM_SYSCLK14_CLKSEL      0x48180370
#define CM_SYSCLK16_CLKSEL      0x48180374
#define CM_SYSCLK18_CLKSEL      0x48180378
#define CM_AUDIOCLK_MCASP0_CLKSEL          0x4818037C
#define CM_AUDIOCLK_MCASP1_CLKSEL          0x48180380
#define CM_AUDIOCLK_MCASP2_CLKSEL          0x48180384
#define CM_AUDIOCLK_MCBSP_CLKSEL           0x48180388

void WR_MEM_32(unsigned int addr, unsigned int data);
unsigned int RD_MEM_32(unsigned int addr);

int CLKIN =	27;

volatile unsigned int *virt_addr;
int us_fd;

void WR_MEM_32(unsigned int addr, unsigned int data)
{
	void *map_base;
	unsigned int data_bs;
	unsigned int data_as;
	unsigned int size;
	off_t target;

	target = addr;
	size = 4;

	/* Map one page */
	map_base = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, us_fd, target & ~MAP_MASK);
	if(map_base == (void *) -1){
		printf ("Could not open the mem file \n");
	}
	printf("data %x\n", data);
	virt_addr = (unsigned int *)(map_base + (target & MAP_MASK));
	data_bs = *virt_addr;
	*virt_addr = data;
	data_as = *virt_addr;

	DISP_ADDRPHY_ADDRVIRT_DATA_BW(target, virt_addr, data_bs);
	DISP_ADDRPHY_ADDRVIRT_DATA_AW(target, virt_addr, data_as);

	munmap(map_base,/*MAP_SIZE */ MAP_SIZE);
}

unsigned int RD_MEM_32(unsigned int addr)
{
	void *map_base;
	unsigned int data;
	unsigned int data_as;
	unsigned int size;
	off_t target;

	target = addr;
	size = 4;

	/* Map one page */
	map_base = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, us_fd, target & ~MAP_MASK);
	if(map_base == (void *) -1) {
		printf ("Could not open the mem file \n");
	}
	virt_addr = (unsigned int*)(map_base + (target & MAP_MASK));
	data = *virt_addr;
	DISP_ADDRPHY_ADDRVIRT_DATA(target, virt_addr, data);

	munmap(map_base,/*MAP_SIZE */ MAP_SIZE);

	return data;
}

void get_powerstate(unsigned int addr)
{
	unsigned int data;
	int powerstate;
	
	data = RD_MEM_32(addr);
	powerstate = data & 0x3u;
	if (powerstate == 0x0u)
		printf("POWERSTATE: %d, OFF State\n\n",powerstate);
	else if (powerstate == 0x3u)
		printf("POWERSTATE: %d, ON State\n\n",powerstate);
}

void get_clocktrctrl(unsigned int addr)
{
	unsigned int data;
	int clocktrctrl;
	
	data = RD_MEM_32(addr);
	clocktrctrl = data & 0x3u;
	if (clocktrctrl == 0x1u)
		printf("CLOCKTRCTRL: %d, SW_SLEEP\n\n",clocktrctrl);
	else if (clocktrctrl == 0x2u)
		printf("CLOCKTRCTRL: %d, SW_WKUP\n\n",clocktrctrl);
}

void get_modulemode(unsigned int addr)
{
	unsigned int data;
	int moduleMode;
	
	data = RD_MEM_32(addr);
	moduleMode = data & 0x3u;
	if (moduleMode == 0x2u)
		printf("MODULEMODE: %d, MODULE ENABLED\n\n",moduleMode);
	else if (moduleMode == 0x0u)
		printf("MODULEMODE: %d, MODULE DISABLED\n\n",moduleMode);
}

void get_powerInfo()
{
	printf("\n*************************ACTIVE DOMAIN**********************\n");
	printf("ACTIVE Power State:\n");
	get_powerstate(PM_ACTIVE_PWRSTCTRL);
	printf("DSP Clock Domain Power State:\n");
	get_clocktrctrl(CM_GEM_CLKCTRL);
	printf("DSP Clock:\n");
	get_modulemode(CM_ACTIVE_GEM_CLKCTRL);
	printf("HDVPSS Clock Domain Power state:\n");
	get_clocktrctrl(CM_HDDSS_CLKCTRL);
	printf("HDVPSS Clock:\n");
	get_modulemode(CM_ACTIVE_HDDSS_CLKCTRL);
	printf("HDMI Clock Domain Power State\n");
	get_clocktrctrl(CM_HDMI_CLKCTRL);
	printf("HDMI Clock:\n");
	get_modulemode(CM_ACTIVE_HDMI_CLKCTRL);
	printf("************************************************************\n");
	
	printf("\n***********************DEFAULT DOMAIN***********************\n");
	printf("DEFAULT Power State:\n");
	get_powerstate(PM_DEFAULT_PWRSTCTRL);
	printf("L3 Medium Clock Domain: \n");
	get_clocktrctrl(CM_DEFAULT_L3_MED_CLKSTCTRL);
	printf("L3 Fast Clock Domain: \n");
	get_clocktrctrl(CM_DEFAULT_L3_FAST_CLKSTCTRL);
	printf("PCI Clock Domain: \n");
	get_clocktrctrl(CM_DEFAULT_PCI_CLKSTCTRL);
	printf("L3 Slow Clock Domain: \n");
	get_clocktrctrl(CM_DEFAULT_L3_SLOW_CLKSTCTRL);
	printf("Default Clock Domain: \n");
	get_clocktrctrl(CM_DEFAULT_CLKSTCTRL);
	printf("EMIF0 Clock:\n");
	get_modulemode(CM_DEFAULT_EMIF_0_CLKCTRL);
	printf("EMIF1 Clock:\n");
	get_modulemode(CM_DEFAULT_EMIF_1_CLKCTRL);
	printf("DMM Clock:\n");
	get_modulemode(CM_DEFAULT_DMM_CLKCTRL);
	printf("EMIF FW Clock:\n");
	get_modulemode(CM_DEFAULT_FW_CLKCTRL);
	printf("USB Clock:\n");
	get_modulemode(CM_DEFAULT_USB_CLKCTRL);
	printf("SATA Clock:\n");
	get_modulemode(CM_DEFAULT_SATA_CLKCTRL);
	printf("PCI Clock:\n");
	get_modulemode(CM_DEFAULT_PCI_CLKCTRL);
	printf("************************************************************\n");
	
	printf("\n***********************IVAHD0 Domain************************\n");
	printf("IVAHD0 Power State:\n");
	get_powerstate(PM_IVAHD0_PWRSTCTRL);
	printf("IVAHD0 Clock Domain Power State:\n");
	get_clocktrctrl(CM_IVAHD0_CLKCTRL);
	printf("HDVICP0 Clock:\n");
	get_modulemode(CM_IVAHD0_IVAHD_CLKCTRL);
	printf("HDVICP0 SL2 Clock:\n");
	get_modulemode(CM_IVAHD0_SL2_CLKCTRL);
	printf("************************************************************\n");

	printf("\n***********************IVAHD1 Domain************************\n");
	printf("IVAHD1 Power State:\n");
	get_powerstate(PM_IVAHD1_PWRSTCTRL);
	printf("IVAHD1 Clock Domain Power State:\n");
	get_clocktrctrl(CM_IVAHD1_CLKCTRL);
	printf("HDVICP1 Clock:\n");
	get_modulemode(CM_IVAHD1_IVAHD_CLKCTRL);
	printf("HDVICP1 SL2 Clock:\n");
	get_modulemode(CM_IVAHD1_SL2_CLKCTRL);
	printf("************************************************************\n");

	printf("\n************************IVAHD2 Domain***********************\n");
	printf("IVAHD2 Power State:\n");
	get_powerstate(PM_IVAHD2_PWRSTCTRL);
	printf("IVAHD2 Clock Domain Power State:\n");
	get_clocktrctrl(CM_IVAHD2_CLKCTRL);
	printf("HDVICP2 Clock:\n");
	get_modulemode(CM_IVAHD2_IVAHD_CLKCTRL);
	printf("HDVICP2 SL2 Clock:\n");
	get_modulemode(CM_IVAHD2_SL2_CLKCTRL);
	printf("************************************************************\n");
	
	printf("\n************************SGX Domain**************************\n");
	printf("SGX Power State:\n");
	get_powerstate(PM_SGX_PWRSTCTRL);
	printf("SGX Clock Domain Power State:\n");
	get_clocktrctrl(CM_SGX_CLKSTCTRL);
	printf("SGX Clock:\n");	
	get_modulemode(CM_SGX_SGX_CLKCTRL);
	printf("************************************************************\n");
}

float readPLL(unsigned int pll_ctrl, unsigned int pll_freq, unsigned int pll_div)
{
	unsigned int mult, div, pre_div, integer, ctrl_reg, freq_reg;
	float frac, freq, value_freq;
	
	ctrl_reg = RD_MEM_32(pll_ctrl);
	if ((ctrl_reg & 0x00000008) == 0x8)
		printf("PLL is enabled\n");
	else
		printf("PLL is disabled\n");

	if ((ctrl_reg & 0x00000004) == 0x4)
		printf("PLL is in normal operation\n");
	else
		printf("PLL is in bypass mode\n");

	freq_reg    = RD_MEM_32(pll_freq);
	mult        = (ctrl_reg & 0xFFFF0000) >> 16;
	pre_div     = (ctrl_reg & 0xFF00)>>8;
	frac        = ((float)(freq_reg & 0xFFFFFF))/ ((float) (0x1000000-1));
	integer     = (freq_reg & 0xF000000) >>24;
	freq        = frac + integer;
	div         = (RD_MEM_32(pll_div) & 0xFF);
	value_freq    = ((float) (27 * mult * 8)) / ((float) ((pre_div * freq) * div));
	return value_freq;
}

void getdivPLL(unsigned int pll_ctrl,unsigned int pll_div)
{
	unsigned int ddr_mult, ddr_div, ddr_pre_div, dmm_int;
	float ddr_freq, dmm_freq, dmm_frac, freq;
	
	ddr_mult    = (RD_MEM_32(pll_ctrl) & 0xFFFF0000)>>16;
	ddr_div     = (RD_MEM_32(pll_div) & 0xFF);
	ddr_pre_div = (RD_MEM_32(pll_ctrl) & 0xFF00)>>8;
	ddr_freq    = (27 * ddr_mult)/(ddr_div * ddr_pre_div);
	printf("\n\nfreq = %f\n", ddr_freq);
}

int main(int argc, char **argv) 
{
	void *map_base;
	unsigned long read_result, writeval;
	unsigned int addr, data;
	int i;

	float freq_sysclk[24], value_freq,  value_freq_B3, value_freq_C1, 
		value_freq_D1, freq_mcasp0, freq_mcasp1, freq_mcasp2, freq_mcbsp;
	int prcm_div[24], prcm_div_B3, prcm_div_C1, prcm_div_D1, 
				mcasp0_clk, mcasp1_clk, mcasp2_clk, mcbsp_clk;
    
	if(argc < 2) {
		printf("Usage: %s [p|f]\n\t p : for module mode\n\t f : for pll frequency",  argv[0]);
		exit(1);
    	}

	if((us_fd = open("/dev/mem", O_RDWR | O_SYNC)) == -1) {
		printf ("Could not open the mem file \n");
	}

	printf("/dev/mem opened.\n");
	switch (argv[1][0]) {
		case 'p':
			printf ("GET PLL Status\n");
			get_powerInfo();
			break;
		case 'f':
			for (i = 0; i < 24; i++)
				prcm_div[i] = -1;

			printf ("PLL Frequency\n");
			printf ("*******************MAINPLL********************\n");

			/* For FREQ1 */
			value_freq = readPLL(MAINPLL_CTRL, MAINPLL_FREQ1, MAINPLL_DIV1);
			printf("\nFREQ1 : %f Mhz\n\n",value_freq);
			prcm_div[0] = (RD_MEM_32(CM_SYSCLK1_CLKSEL) & 0x07) + 1;
			freq_sysclk[0] = value_freq / ((float) prcm_div[0]);
			printf("\nSYSCLK1 (DSP)\t: %f Mhz\n\n", freq_sysclk[0]);
			printf("-----------------------------------------------------\n");
			
			/* For FREQ2 */
			value_freq = readPLL(MAINPLL_CTRL, MAINPLL_FREQ2, MAINPLL_DIV2);
			printf("\nFREQ2 : %f Mhz\n\n",value_freq);
			prcm_div[1] = (RD_MEM_32(CM_SYSCLK2_CLKSEL) & 0x07) + 1;
			freq_sysclk[1] = value_freq / ((float) prcm_div[1]);
			printf("\nSYSCLK2 (A8)\t: %f Mhz\n\n",freq_sysclk[1]);
			prcm_div[22] = (RD_MEM_32(CM_SYSCLK23_CLKSEL) & 0x07) + 1;
			freq_sysclk[22] = value_freq / ((float) prcm_div[22]);
			printf("\nSYSCLK23 (SGX)\t: %f Mhz\n\n",freq_sysclk[22]);
			printf("-----------------------------------------------------\n");

			/* For FREQ3 */
			value_freq = readPLL(MAINPLL_CTRL, MAINPLL_FREQ3, MAINPLL_DIV3);
			printf("\nFREQ3 : %f Mhz\n\n",value_freq);
			prcm_div[2] = (RD_MEM_32(CM_SYSCLK3_CLKSEL) & 0x07) + 1;
			freq_sysclk[2] = value_freq / ((float) prcm_div[2]);
			printf("\nSYSCLK3 (hdvicp2)\t: %f Mhz\n\n",freq_sysclk[2]);
			printf("-----------------------------------------------------\n");

			/* For FREQ4 */
			value_freq = readPLL(MAINPLL_CTRL, MAINPLL_FREQ4, MAINPLL_DIV4);
			printf("\nFREQ4 : %f Mhz\n\n",value_freq);
			prcm_div[3] = (RD_MEM_32(CM_SYSCLK4_CLKSEL) & 0x01) + 1;
			freq_sysclk[3] = value_freq / ((float) prcm_div[3]);
			printf("\nSYSCLK4 \t: %f Mhz\n\n",freq_sysclk[3]);
			prcm_div[4] = (RD_MEM_32(CM_SYSCLK5_CLKSEL) & 0x01) + 1;
			freq_sysclk[4] = freq_sysclk[3] / ((float) prcm_div[4]);
			printf("\nSYSCLK5 \t: %f Mhz\n\n", freq_sysclk[4]);
			prcm_div[5] = ((RD_MEM_32(CM_SYSCLK6_CLKSEL) & 0x01) + 1) * 2;
			freq_sysclk[5] = freq_sysclk[3] / ((float) prcm_div[5]);
			printf("\nSYSCLK6 \t: %f Mhz\n\n",freq_sysclk[5]);
			prcm_div[6] = (RD_MEM_32(CM_SYSCLK7_CLKSEL) & 0x03);
			if (prcm_div[6] == 0)
				prcm_div[6] = 5;
			else if (prcm_div[6] == 1)
				prcm_div[6] = 6;
			else if (prcm_div[6] == 2)
				prcm_div[6] = 8;
			else if (prcm_div[6] == 3)
				prcm_div[6] = 16;

			freq_sysclk[6] = freq_sysclk[3] / ((float) prcm_div[6]);
			printf("\nSYSCLK7 \t: %f Mhz\n\n",freq_sysclk[6]);
			printf("-----------------------------------------------------\n");

			/* For FREQ5 */
			value_freq = readPLL(MAINPLL_CTRL, MAINPLL_FREQ5, MAINPLL_DIV5);
			printf("\nFREQ5 : %f Mhz\n\n",value_freq);
			prcm_div[23] = (RD_MEM_32(CM_SYSCLK24_CLKSEL) & 0x07) + 1;
			freq_sysclk[23] = value_freq / ((float) prcm_div[23]);
			printf("\nSYSCLK24 (EMAC)\t: %f Mhz\n\n",freq_sysclk[23]);
			printf("-----------------------------------------------------\n");

			printf("\nUSB Clock\n");
			getdivPLL(MAINPLL_CTRL, MAINPLL_DIV6);
			printf("\nAUDIO PLL Reference clock\n");
			getdivPLL(MAINPLL_CTRL, MAINPLL_DIV7);
			printf("-----------------------------------------------------\n");

			printf ("*******************DDRPLL********************\n");

			/* For FREQ2 */
			value_freq = readPLL(DDRPLL_CTRL, DDRPLL_FREQ2, DDRPLL_DIV2);
			printf("\nFREQ2 : %f Mhz\n\n",value_freq);
			prcm_div[9] = (RD_MEM_32(CM_SYSCLK10_CLKSEL) & 0x01) + 1;
			freq_sysclk[9] = value_freq / ((float) prcm_div[9]);
			printf("\nSYSCLK10 (SPI,I2C,SD,UART): %f Mhz\n\n",freq_sysclk[9]);
			freq_sysclk[8] = freq_sysclk[9] / 3;
			printf("\nSYSCLK9 (CEC CLOCK)\t: %f Mhz\n\n",freq_sysclk[8]);
			printf("-----------------------------------------------------\n");

			/* For FREQ3 */
			value_freq = readPLL(DDRPLL_CTRL, DDRPLL_FREQ3, DDRPLL_DIV3);
			printf("\nFREQ3 : %f Mhz\n\n",value_freq);
			freq_sysclk[7] = value_freq;/* default and only value of divider is 1 */
			printf("\nSYSCLK8 : %f Mhz\n\n",freq_sysclk[7]);
			printf("-----------------------------------------------------\n");

			getdivPLL(DDRPLL_CTRL, DDRPLL_DIV1);
			printf("-----------------------------------------------------\n");

			printf ("\n*******************VIDEOPLL********************\n");
			/* For FREQ1 */
			value_freq = readPLL(VIDEOPLL_CTRL, VIDEOPLL_FREQ1, VIDEOPLL_DIV1);
			printf("\nFREQ1 : %f Mhz\n\n",value_freq);
			prcm_div[10] = (RD_MEM_32(CM_SYSCLK11_CLKSEL) & 0x01) + 1;
			freq_sysclk[10] = value_freq / ((float) prcm_div[10]);
			printf("\nSYSCLK11 : %f Mhz\n\n", freq_sysclk[10]);
			prcm_div_D1 = (RD_MEM_32(CM_VPD1_CLKSEL) & 0x07) + 1;
			value_freq_D1 = value_freq / ((float) prcm_div_D1);
			printf("-----------------------------------------------------\n");
			
			/* For FREQ2 */
			value_freq = readPLL(VIDEOPLL_CTRL, VIDEOPLL_FREQ2, VIDEOPLL_DIV2);
			printf("\nFREQ2 : %f Mhz\n\n",value_freq);
			prcm_div[12] = (RD_MEM_32(CM_SYSCLK13_CLKSEL) & 0x07) + 1;
			freq_sysclk[12] = value_freq / ((float) prcm_div[12]);
			printf("\nSYSCLK13 (HD_VENC_D_CLK): %f Mhz\n\n",freq_sysclk[12]);
			printf("-----------------------------------------------------\n");
			prcm_div_B3 = (RD_MEM_32(CM_VPB3_CLKSEL) & 0x03);
			if (prcm_div_B3 == 0)
				prcm_div_B3 = 1;
			else if (prcm_div_B3 == 1)
				prcm_div_B3 = 2;
			if (prcm_div_B3 == 2)
				prcm_div_B3 = 22;
			
			value_freq_B3 = value_freq / ((float) prcm_div_B3);
			
			/* For FREQ3 */
			value_freq = readPLL(VIDEOPLL_CTRL, VIDEOPLL_FREQ3, VIDEOPLL_DIV3);
			printf("\nFREQ3 : %f Mhz\n\n",value_freq);
			prcm_div[14] = (RD_MEM_32(CM_SYSCLK15_CLKSEL) & 0x07) + 1;
			freq_sysclk[14] = value_freq / ((float) prcm_div[14]);
			printf("\nSYSCLK15 (HD_VENC_A_CLK): %f Mhz\n\n",freq_sysclk[14]);

			prcm_div_C1 = (RD_MEM_32(CM_VPC1_CLKSEL) & 0x03);
			if (prcm_div_C1 == 0)
				prcm_div_C1 = 1;
			else if (prcm_div_C1 == 1)
				prcm_div_C1 = 2;
			if (prcm_div_C1 == 2)
				prcm_div_C1 = 22;
			
			value_freq_C1 = value_freq / ((float) prcm_div_C1);

			printf("-----------------------------------------------------\n");
			
			prcm_div[13] = (RD_MEM_32(CM_SYSCLK14_CLKSEL) & 0x03);
			if (prcm_div[13] == 0)
				freq_sysclk[13] = value_freq_B3;
			else if (prcm_div[13] == 1)
				freq_sysclk[13] = CLKIN;
			else if (prcm_div[13] == 2)
				freq_sysclk[13] = value_freq_C1;
			printf("\nSYSCLK14 : %f Mhz\n\n", freq_sysclk[13]);

			prcm_div[15] = (RD_MEM_32(CM_SYSCLK16_CLKSEL) & 0x01);
			if (prcm_div[15] == 0)
				freq_sysclk[15] = value_freq_D1;
			else if (prcm_div[15] == 1)
				freq_sysclk[15] = value_freq_B3;
				
			printf("\nSYSCLK16 : %f Mhz\n\n", freq_sysclk[15]);
			printf("-----------------------------------------------------\n");

			printf ("*******************AUDIOPLL********************\n");
			/* For FREQ2 */
			value_freq = readPLL(AUDIOPLL_CTRL, AUDIOPLL_FREQ2, AUDIOPLL_DIV2);
			printf("\nFREQ2 : %f Mhz\n\n",value_freq);
			prcm_div[18] = (RD_MEM_32(CM_SYSCLK19_CLKSEL) & 0x07) + 1;
			freq_sysclk[18] = value_freq / ((float) prcm_div[18]);
			printf("\nSYSCLK19 : %f Mhz\n\n",freq_sysclk[18]);
			printf("-----------------------------------------------------\n");

			/* For FREQ3 */
			value_freq = readPLL(AUDIOPLL_CTRL, AUDIOPLL_FREQ3, AUDIOPLL_DIV3);
			prcm_div[19] = (RD_MEM_32(CM_SYSCLK20_CLKSEL) & 0x07) + 1;
			freq_sysclk[19] = value_freq / ((float) prcm_div[19]);
			printf("\nSYSCLK20 : %f Mhz\n\n",freq_sysclk[19]);
			printf("-----------------------------------------------------\n");

			/* For FREQ4 */
			value_freq = readPLL(AUDIOPLL_CTRL, AUDIOPLL_FREQ4, AUDIOPLL_DIV4);
			printf("\nFREQ4 : %f Mhz\n\n",value_freq);
			prcm_div[20] = (RD_MEM_32(CM_SYSCLK21_CLKSEL) & 0x07) + 1;
			freq_sysclk[20] = value_freq / ((float) prcm_div[20]);
			printf("\nSYSCLK21 : %f Mhz\n\n",freq_sysclk[20]);
			printf("-----------------------------------------------------\n");

			/* For FREQ5 */
			value_freq = readPLL(AUDIOPLL_CTRL, AUDIOPLL_FREQ5, AUDIOPLL_DIV5);
			printf("\nFREQ5 : %f Mhz\n\n",value_freq);
			prcm_div[21] = (RD_MEM_32(CM_SYSCLK22_CLKSEL) & 0x07) + 1;
			freq_sysclk[21] = value_freq / ((float) prcm_div[21]);
			printf("\nSYSCLK22 : %f Mhz\n\n",freq_sysclk[21]);
			printf("-----------------------------------------------------\n");

			mcasp0_clk = RD_MEM_32(CM_AUDIOCLK_MCASP0_CLKSEL) & 0x03;
			switch(mcasp0_clk)
			{
			   case 0:
			   	freq_mcasp0 = freq_sysclk[19];
			   case 1:
			   	freq_mcasp0 = freq_sysclk[20];
			   case 2:
			   	freq_mcasp0 = freq_sysclk[21];
			}
			printf("\nMCASP0 CLK = %f\n", freq_mcasp0);

			mcasp1_clk = RD_MEM_32(CM_AUDIOCLK_MCASP1_CLKSEL) & 0x03;
			switch(mcasp1_clk)
			{
			   case 0:
			   	freq_mcasp1 = freq_sysclk[19];
			   case 1:
			   	freq_mcasp1 = freq_sysclk[20];
			   case 2:
			   	freq_mcasp1 = freq_sysclk[21];
			}
			printf("\nMCASP1 CLK = %f\n", freq_mcasp1);
			
			mcasp2_clk = RD_MEM_32(CM_AUDIOCLK_MCASP2_CLKSEL) & 0x03;
			switch(mcasp2_clk)
			{
			   case 0:
			   	freq_mcasp2 = freq_sysclk[19];
			   case 1:
			   	freq_mcasp2 = freq_sysclk[20];
			   case 2:
			   	freq_mcasp2 = freq_sysclk[21];
			}
			printf("\nMCASP2 CLK = %f\n", freq_mcasp2);

			mcbsp_clk = RD_MEM_32(CM_AUDIOCLK_MCBSP_CLKSEL) & 0x03;
			switch(mcbsp_clk)
			{
			   case 0:
			   	freq_mcbsp = freq_sysclk[19];
			   case 1:
			   	freq_mcbsp = freq_sysclk[20];
			   case 2:
			   	freq_mcbsp = freq_sysclk[21];
			}
			printf("\nMCBSP CLK = %f\n", freq_mcbsp);

			break;
			
	      	default:
			printf ("Choose right option\n");
			break;
    }

    close(us_fd);
}

0 kisung cho over 12 years ago in reply to Badri Narayanan

Expert 1460 points

Hi.

i printed PLL setting. but i can't see any strange thing. there is no way avoid AVSYNC issue? .

/dev/mem opened.
PLL Frequency
*******************MAINPLL********************
Phy Addr : 0x48140400 Data : 0x00380188
PLL is enabled
PLL is in bypass mode
Phy Addr : 0x48140408 Data : 0x9f1eb851
Phy Addr : 0x4814040c Data : 0x00000101

FREQ1 : 800.000000 Mhz

Phy Addr : 0x48180300 Data : 0x00000000

SYSCLK1 (DSP) : 800.000000 Mhz

-----------------------------------------------------
Phy Addr : 0x48140400 Data : 0x00380188
PLL is enabled
PLL is in bypass mode
Phy Addr : 0x48140410 Data : 0x9c189374
Phy Addr : 0x48140414 Data : 0x00000101

FREQ2 : 1000.000000 Mhz

Phy Addr : 0x48180304 Data : 0x00000000

SYSCLK2 (A8) : 1000.000000 Mhz

Phy Addr : 0x481803b0 Data : 0x00000003

SYSCLK23 (SGX) : 250.000000 Mhz

-----------------------------------------------------
Phy Addr : 0x48140400 Data : 0x00380188
PLL is enabled
PLL is in bypass mode
Phy Addr : 0x48140418 Data : 0x9a147ae1
Phy Addr : 0x4814041c Data : 0x00000102

FREQ3 : 600.000000 Mhz

Phy Addr : 0x48180308 Data : 0x00000000

SYSCLK3 (hdvicp2) : 600.000000 Mhz

-----------------------------------------------------
Phy Addr : 0x48140400 Data : 0x00380188
PLL is enabled
PLL is in bypass mode
Phy Addr : 0x48140420 Data : 0x9acccccc
Phy Addr : 0x48140424 Data : 0x00000102

FREQ4 : 560.000000 Mhz

Phy Addr : 0x4818030c Data : 0x00000000

SYSCLK4 : 560.000000 Mhz

Phy Addr : 0x48180310 Data : 0x00000001

SYSCLK5 : 280.000000 Mhz

Phy Addr : 0x48180314 Data : 0x00000001

SYSCLK6 : 140.000000 Mhz

Phy Addr : 0x48180318 Data : 0x00000000

SYSCLK7 : 112.000000 Mhz

-----------------------------------------------------
Phy Addr : 0x48140400 Data : 0x00380188
PLL is enabled
PLL is in bypass mode
Phy Addr : 0x48140428 Data : 0x9c189374
Phy Addr : 0x4814042c Data : 0x00000108

FREQ5 : 125.000000 Mhz

Phy Addr : 0x481803b4 Data : 0x00000000

SYSCLK24 (EMAC) : 125.000000 Mhz

-----------------------------------------------------

USB Clock
Phy Addr : 0x48140400 Data : 0x00380188
Phy Addr : 0x48140434 Data : 0x0000013f
Phy Addr : 0x48140400 Data : 0x00380188

freq = 24.000000

AUDIO PLL Reference clock
Phy Addr : 0x48140400 Data : 0x00380188
Phy Addr : 0x4814043c Data : 0x00000104
Phy Addr : 0x48140400 Data : 0x00380188

freq = 378.000000
-----------------------------------------------------
*******************DDRPLL********************
Phy Addr : 0x48140440 Data : 0x003b018c
PLL is enabled
PLL is in normal operation
Phy Addr : 0x48140450 Data : 0x98d99999
Phy Addr : 0x48140454 Data : 0x0000011e

FREQ2 : 48.000000 Mhz

Phy Addr : 0x48180324 Data : 0x00000000

SYSCLK10 (SPI,I2C,SD,UART): 48.000000 Mhz

SYSCLK9 (CEC CLOCK) : 16.000000 Mhz

-----------------------------------------------------
Phy Addr : 0x48140440 Data : 0x003b018c
PLL is enabled
PLL is in normal operation
Phy Addr : 0x48140458 Data : 0x98000000
Phy Addr : 0x4814045c Data : 0x00000104

FREQ3 : 398.250000 Mhz

SYSCLK8 : 398.250000 Mhz

-----------------------------------------------------
Phy Addr : 0x48140440 Data : 0x003b018c
Phy Addr : 0x4814044c Data : 0x00000102
Phy Addr : 0x48140440 Data : 0x003b018c

freq = 796.000000
-----------------------------------------------------

*******************VIDEOPLL********************
Phy Addr : 0x48140470 Data : 0x006e0288
PLL is enabled
PLL is in bypass mode
Phy Addr : 0x48140478 Data : 0x8dc00000
Phy Addr : 0x4814047c Data : 0x00000104

FREQ1 : 216.000000 Mhz

Phy Addr : 0x4818032c Data : 0x00000000

SYSCLK11 : 216.000000 Mhz

Phy Addr : 0x48180348 Data : 0x00000007
-----------------------------------------------------
Phy Addr : 0x48140470 Data : 0x006e0288
PLL is enabled
PLL is in bypass mode
Phy Addr : 0x48140480 Data : 0x8f3b13b1
Phy Addr : 0x48140484 Data : 0x0000010c

FREQ2 : 65.000000 Mhz

Phy Addr : 0x48180334 Data : 0x00000000

SYSCLK13 (HD_VENC_D_CLK): 65.000000 Mhz

-----------------------------------------------------
Phy Addr : 0x48180340 Data : 0x00000002
Phy Addr : 0x48140470 Data : 0x006e0288
PLL is enabled
PLL is in bypass mode
Phy Addr : 0x48140488 Data : 0x8a000000
Phy Addr : 0x4814048c Data : 0x00000108

FREQ3 : 148.500000 Mhz

Phy Addr : 0x48180338 Data : 0x00000000

SYSCLK15 (HD_VENC_A_CLK): 148.500000 Mhz

Phy Addr : 0x48180344 Data : 0x00000003
-----------------------------------------------------
Phy Addr : 0x48180370 Data : 0x00000000

SYSCLK14 : 2.954545 Mhz

Phy Addr : 0x48180374 Data : 0x00000000

SYSCLK16 : 27.000000 Mhz

-----------------------------------------------------
*******************AUDIOPLL********************
Phy Addr : 0x481404a0 Data : 0x00401988
PLL is enabled
PLL is in bypass mode
Phy Addr : 0x481404b0 Data : 0x8e000000
Phy Addr : 0x481404b4 Data : 0x00000104

FREQ2 : 9.874286 Mhz

Phy Addr : 0x4818034c Data : 0x00000000

SYSCLK19 : 9.874286 Mhz

-----------------------------------------------------
Phy Addr : 0x481404a0 Data : 0x00401988
PLL is enabled
PLL is in bypass mode
Phy Addr : 0x481404b8 Data : 0x89000000
Phy Addr : 0x481404bc Data : 0x00000105
Phy Addr : 0x48180350 Data : 0x00000006

SYSCLK20 : 1.755429 Mhz

-----------------------------------------------------
Phy Addr : 0x481404a0 Data : 0x00401988
PLL is enabled
PLL is in bypass mode
Phy Addr : 0x481404c0 Data : 0x89cbc148
Phy Addr : 0x481404c4 Data : 0x00000114

FREQ4 : 2.822400 Mhz

Phy Addr : 0x48180354 Data : 0x00000000

SYSCLK21 : 2.822400 Mhz

-----------------------------------------------------
Phy Addr : 0x481404a0 Data : 0x00401988
PLL is enabled
PLL is in bypass mode
Phy Addr : 0x481404c8 Data : 0x8d800000
Phy Addr : 0x481404cc Data : 0x00000114

FREQ5 : 2.048000 Mhz

Phy Addr : 0x48180358 Data : 0x00000000

SYSCLK22 : 2.048000 Mhz

-----------------------------------------------------
Phy Addr : 0x4818037c Data : 0x00000000

MCASP0 CLK = 2.048000
Phy Addr : 0x48180380 Data : 0x00000000

MCASP1 CLK = 2.048000
Phy Addr : 0x48180384 Data : 0x00000000

MCASP2 CLK = 2.048000
Phy Addr : 0x48180388 Data : 0x00000002

MCBSP CLK = 2.048000

---------------------------------------------------------------------------------------------------------

/dev/mem opened.
GET PLL Status

*************************ACTIVE DOMAIN**********************
ACTIVE Power State:
Phy Addr : 0x48180a00 Data : 0x00030000
POWERSTATE: 0, OFF State

DSP Clock Domain Power State:
Phy Addr : 0x48180400 Data : 0x00000702
CLOCKTRCTRL: 2, SW_WKUP

DSP Clock:
Phy Addr : 0x48180420 Data : 0x00000002
MODULEMODE: 2, MODULE ENABLED

HDVPSS Clock Domain Power state:
Phy Addr : 0x48180404 Data : 0x0000ff02
CLOCKTRCTRL: 2, SW_WKUP

HDVPSS Clock:
Phy Addr : 0x48180424 Data : 0x00000002
MODULEMODE: 2, MODULE ENABLED

HDMI Clock Domain Power State
Phy Addr : 0x48180408 Data : 0x00000302
CLOCKTRCTRL: 2, SW_WKUP

HDMI Clock:
Phy Addr : 0x48180428 Data : 0x00000002
MODULEMODE: 2, MODULE ENABLED

************************************************************

***********************DEFAULT DOMAIN***********************
DEFAULT Power State:
Phy Addr : 0x48180b00 Data : 0x00030000
POWERSTATE: 0, OFF State

L3 Medium Clock Domain:
Phy Addr : 0x48180504 Data : 0x00000102
CLOCKTRCTRL: 2, SW_WKUP

L3 Fast Clock Domain:
Phy Addr : 0x48180508 Data : 0x00000302
CLOCKTRCTRL: 2, SW_WKUP

PCI Clock Domain:
Phy Addr : 0x48180510 Data : 0x00000002
CLOCKTRCTRL: 2, SW_WKUP

L3 Slow Clock Domain:
Phy Addr : 0x48180514 Data : 0x00000102
CLOCKTRCTRL: 2, SW_WKUP

Default Clock Domain:
Phy Addr : 0x48180518 Data : 0x00000702
CLOCKTRCTRL: 2, SW_WKUP

EMIF0 Clock:
Phy Addr : 0x48180520 Data : 0x00000002
MODULEMODE: 2, MODULE ENABLED

EMIF1 Clock:
Phy Addr : 0x48180524 Data : 0x00000002
MODULEMODE: 2, MODULE ENABLED

DMM Clock:
Phy Addr : 0x48180528 Data : 0x00000002
MODULEMODE: 2, MODULE ENABLED

EMIF FW Clock:
Phy Addr : 0x4818052c Data : 0x00000002
MODULEMODE: 2, MODULE ENABLED

USB Clock:
Phy Addr : 0x48180558 Data : 0x00000002
MODULEMODE: 2, MODULE ENABLED

SATA Clock:
Phy Addr : 0x48180560 Data : 0x00000002
MODULEMODE: 2, MODULE ENABLED

PCI Clock:
Phy Addr : 0x48180578 Data : 0x00070000
MODULEMODE: 0, MODULE DISABLED

************************************************************

***********************IVAHD0 Domain************************
IVAHD0 Power State:
Phy Addr : 0x48180c00 Data : 0x00030000
POWERSTATE: 0, OFF State

IVAHD0 Clock Domain Power State:
Phy Addr : 0x48180600 Data : 0x00000102
CLOCKTRCTRL: 2, SW_WKUP

HDVICP0 Clock:
Phy Addr : 0x48180620 Data : 0x00040002
MODULEMODE: 2, MODULE ENABLED

HDVICP0 SL2 Clock:
Phy Addr : 0x48180624 Data : 0x00000002
MODULEMODE: 2, MODULE ENABLED

************************************************************

***********************IVAHD1 Domain************************
IVAHD1 Power State:
Phy Addr : 0x48180d00 Data : 0x00030000
POWERSTATE: 0, OFF State

IVAHD1 Clock Domain Power State:
Phy Addr : 0x48180700 Data : 0x00000102
CLOCKTRCTRL: 2, SW_WKUP

HDVICP1 Clock:
Phy Addr : 0x48180720 Data : 0x00040002
MODULEMODE: 2, MODULE ENABLED

HDVICP1 SL2 Clock:
Phy Addr : 0x48180724 Data : 0x00000002
MODULEMODE: 2, MODULE ENABLED

************************************************************

************************IVAHD2 Domain***********************
IVAHD2 Power State:
Phy Addr : 0x48180e00 Data : 0x00030000
POWERSTATE: 0, OFF State

IVAHD2 Clock Domain Power State:
Phy Addr : 0x48180800 Data : 0x00000102
CLOCKTRCTRL: 2, SW_WKUP

HDVICP2 Clock:
Phy Addr : 0x48180820 Data : 0x00040002
MODULEMODE: 2, MODULE ENABLED

HDVICP2 SL2 Clock:
Phy Addr : 0x48180824 Data : 0x00000002
MODULEMODE: 2, MODULE ENABLED

************************************************************

************************SGX Domain**************************
SGX Power State:
Phy Addr : 0x48180f00 Data : 0x00030000
POWERSTATE: 0, OFF State

SGX Clock Domain Power State:
Phy Addr : 0x48180900 Data : 0x00000002
CLOCKTRCTRL: 2, SW_WKUP

SGX Clock:
Phy Addr : 0x48180920 Data : 0x00070000
MODULEMODE: 0, MODULE DISABLED

************************************************************

0 Badri Narayanan over 12 years ago in reply to kisung cho

TI__Guru 59700 points

Thanks for providing the PLL info. The PLL setting are fine. This is most likely due to VIP reset ISR happening continuously. Pls confirm you are on RDK v3.0.1 ? We will provide a HDVPSS driver ptach to disable VIP reset ISR .

Sujith,

Can you pls share the VIP reset HDVPSS patch

0 kisung cho over 12 years ago in reply to Badri Narayanan

Expert 1460 points

To. Badri Narayanan.

Thanks for your replay.

currently i'm using RDK03.00.00 from udworks.

i'm very glad to figure out this issue. can i get RDK03.00.00 patch?

would you explain why VIP reset ISR happening continuously?

Regards. CHO

0 Sujith over 12 years ago in reply to kisung cho

TI__Genius 12455 points

Hello CHO,

The HDVPSS used in RDK 03.0 had enabled VIP interrupt, which is not required for PG 2.0 and later. The attached patches, will conditionally enable the VIP interrupt. We suspect these interrupt is causing the issue that you are seeing.

Please apply these patches on HDVPSS, perform a clean build and re-check.

Thanks,

Sujith

1832.VIP_InterruptMaskPatches.zip

0 kisung cho over 12 years ago in reply to Sujith

Expert 1460 points

Hello Sujith.

thanks for your patch.

I applied this patch. i tested connect/disconnect (BNC) by hand, there no more "AVSYNC error" . thanks.

But I aging tested 8 SET DVR during two days. 2 SET 's encoding data is not captured then rebooted.

before apply this patch, there was only "AVSYNC error" . is there any side effects or another problem ?

how can i fix it?

i attached 2SET LOG

0753.201210120047.pdf

7840.201210120048.pdf

5633.201210120107.pdf

Regards. CHO

0 Badri Narayanan over 12 years ago in reply to kisung cho

TI__Guru 59700 points

Mr.Cho,

I am seeing warnings of the form "ENCLINK:H264Enc !!WARNING!!!Unable to handle runtime output buffer". This indicates the encoded frame size is greater than allocated size. What is the input resolution and bitrate that you are setting ? Also do you see encode stopping for all channels or only for some channels

0 kisung cho over 12 years ago in reply to Badri Narayanan

Expert 1460 points

Hello. Thanks for your Reply.

Because "AV Sync"issue , i setted DVR's bitrate to 1000 Kbps in CH1~CH16.

I know that mcfw default bitrate is 2000 Kbps, but when i set low bitrate i can see low quality encoded video.

i tested encoding bitrate is working .

[m3video] 18633: ENCODE: Creating CH0 of 704 x 480, pitch = (16384, 32768) [PROGRESSIVE] [TILED ], bitrate = 1000 Kbps ...

i attached Vsys_printDetailedStatics result and test screen(DVD video and TV video). this issue is occured in dark night( 0, 1, 2 hour).

Do you think dark night noise and DVD video is an indirect cause of this issue?

anyway i will test 2000 Kbps setting is good in the weekend.

Any advise will be appreciated.

4442.201210121651.pdf

Regards . CHO

0 kisung cho over 12 years ago in reply to kisung cho

Expert 1460 points

Hi Narayanan.

i tested 2000 Kbps setting will be good or not , in the last weekend( 3days aging).

but it's more worst result(more frequently ENC buffer error - three times occur one day) then setting 1000 Kbps encode bitrate(most one or two times occur one day).

how can i fix it?(it only occured NTSC signal, i aginged another 2 SET PAL signal , there was no problem. but PAL input only low bitrate camera input )

attached my aging log

1856.201210140206.pdf

4666.201210140951.pdf

6471.201210140952.pdf

Thanks.

CHO

0 Badri Narayanan over 12 years ago in reply to kisung cho

TI__Guru 59700 points

Can you pls provide the encoder settings. Are you using VBR or CBR ? In the encoded stream are you seeing target bitrate being achieved. Also can you try changing

/dvr_rdk/mcfw/src_bios6/links_m3video/codec_utils/utils_encdec.h

Change

#define UTILS_ENCDEC_GET_BITBUF_SIZE(width,height,bitrate,framerate) (((width) * (height))/2)

#define UTILS_ENCDEC_GET_BITBUF_SIZE(width,height,bitrate,framerate) (((width) * (height)))

Note that this will increase the bitstream buffer size.Also I want to confirm you are using RDK v3.0

0 kisung cho over 12 years ago in reply to Badri Narayanan

Expert 1460 points

Hi Narayanan.

Thanks for your reply.

currently my rdk directory name is DVRRDK_V03.00.00.00(udworks)

below is my bitrate setting code.

<code>

for(i = 0 ; i < pContext->venc.numPrimaryChn; i++){
/*Enabling generation of motion vector for channel 0 only,
* for other channels please add to the below line*/
pContext->venc.encChannelParams[i].enableAnalyticinfo = 0;
pContext->venc.encChannelParams[i].rcType = VENC_RATE_CTRL_VBR;
pContext->venc.encChannelParams[i].dynamicParam.frameRate = 15*1000;

if(pContext->nSignal == VSYS_STD_PAL){
pContext->venc.encChannelParams[i].dynamicParam.targetBitRate = 2000*1000;
}else{
pContext->venc.encChannelParams[i].dynamicParam.targetBitRate = 2000*1000;
}
pContext->venc.encChannelParams[i].dynamicParam.intraFrameInterval = 15;
pContext->venc.encChannelParams[i].maxBitRate = -1;
printf("[%s]encChannelParams setting:%d\n", __func__, i);

}

Venc_init(&pContext->venc);

</code>

and it's my fps setting code.

Is there any problem that i must setting target bitrate when i set fps ?

like this( " params.targetBitRate = nFps*1000; ") must add targetBitRate setting whenever VENC_FRAMERATE set.

<code>

void ti_encode_set_fps(int chid, int nFps)
{

VENC_CHN_DYNAMIC_PARAM_S params;
memset(&params, 0, sizeof(VENC_CHN_DYNAMIC_PARAM_S));
if(nFps <= 0 || nFps > 30){
return ;
}
memset(&params, 0, sizeof(params));
params.frameRate = nFps;

Venc_setDynamicParam(chid, 0, &params, VENC_FRAMERATE);
}

</code>

it's my Vsys_printDetailedStatics log. and is there any function check current bitrate ? how can i check the bitrate problem?(some advise needs)

finally i will check and aging " #define UTILS_ENCDEC_GET_BITBUF_SIZE(width,height,bitrate,framerate) (((width) * (height)))"

0 Badri Narayanan over 12 years ago in reply to kisung cho

TI__Guru 59700 points

The setting of frame rate from application is correct.If you dont want to change bitrate set it to zero as you have done in your application. What is the frame rate and bitrate in your application when you see the issue. Are you seeing the issue when you use CBR instead of VBR ? To check the bitrate generated, accumulate the number of bytes generated per encoded frame VCODEC_BITSBUF_S.filledBufSize and average over each second.This should match your target bitrate setting

0 Marat Shchuchinsky over 12 years ago in reply to Sujith

Expert 2595 points

Hello Sujith.

Is this possible fix this issue "AVSYNC error" with DVR-RDK 02.00.00.24 for DM8168?

0 kisung cho over 12 years ago in reply to Marat Shchuchinsky

Expert 1460 points

Hi Narayanan.

as you mentioned above, i modified " #define UTILS_ENCDEC_GET_BITBUF_SIZE(width,height,bitrate,framerate) (((width) * (height)))"

i tested 3 days aging. there is no more "ENCLINK:H264Enc !!WARNING!!!Unable to handle runtime output buffer".

customer's filed env is very different, matching target bitrate is difficult.

anyway " #define UTILS_ENCDEC_GET_BITBUF_SIZE(width,height,bitrate,framerate) (((width) * (height)))" works good.

Thank you very much for your help.

Regargs.

CHO.

Processors

Processors forum

AVSYNC error . how can i reset m3vpss ?