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dmtimer can't go faster than 50KHz

Hello,

embedded newbie so please forgive stupid questions.

I have a hard realtime application that I need to run at 100KHz, the computation that needs to occur between steps takes about 4us on a beaglebone (benchmarked under linux). Linux doesn't come close to providing the time step reliability so I'm looking at starterware. 

I'm playing with dmtimerCounter demo. I've removed the UART writes from DMTimerIsr but it is otherwise unmodified other than changing counters. The ISR does very little, it disables timer interrupts, clears the interrupt, decrements a counter and re-enables interrupts.The main program blocks with a while loop that is waiting for the counter to hit zero. It works fine to about 50KHz, but faster than that and the counter wraps before the while loop reacts, ie the counter (an unsigned int) goes through zero and starts again at the max value. It seems the main thread is starved because of overhead handling the interrupt.

This seems to be very poor performance for a 700MHz processor. Is this the best I can expect or am I doing something seriously wrong?

Thanks,

Evan.

  • Following another thread I enabled the MMU using a routine MMUConfigAndEnable that I found in another example, and enabled the cache using CacheEnable(CACHE_ALL). I'm now able to run the timer at 250+ KHz however it still seems close to saturating the system. When I include a 7us calculation between timer ticks, outside the interrupt, it fails even at 100KHz even though the previous data suggests that this should work (just). Is there an interaction between cache, interrupt code and normal code?

    Any advice gratefully appreciated,

    Thanks,

    Evan.

  • I don't know if it makes up the difference, but the beaglebone running on USB power is only running at 500MHz.

  • I thought that was just a linux thing. In any case I have 5V DC power supply attached.

    Thanks,

    Evan.