This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Mipi DSI settings on ILI9486 panel

Other Parts Discussed in Thread: 4460, SYSCONFIG

Hi

ILI9486 panel datasheet please refer

http://www.displayfuture.com/Display/datasheet/controller/ILI9486.pdf

Could you teach me how to fill the parameter about dispc and dsi clock settings on Board-omap4panda.c file. (ILI9486 panel)

We haven't seem any frame on panel.

But pixel data have beed sent by panda board DSI data lane (scope have waveform).

 

Initial code have already done on panel. (we have measure the voltage . it is correct)

 

here is our setting below.

static struct omap_dss_device panda4460_lcd_device = {
 .name   = "lcd",
 .driver_name  = "ili9486_dsi",
 .type   = OMAP_DISPLAY_TYPE_DSI,
 .data   = &dsi1_panel_data,
 .phy.dsi  = {
  .type = OMAP_DSS_DSI_TYPE_VIDEO_MODE,
  .clk_lane = 1,
  .clk_pol = 0,
  .data1_lane = 2,
  .data1_pol = 0,
 },
  
 .clocks = {
  .dispc = {
   .channel = {


    .lck_div = 1, /* LCD */// Logic clk 144MHz
    .pck_div = 14, /* PCD */ //10.28MHz
 
    .lcd_clk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
   },
   .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK,
  },

  .dsi = {
  
   .regn  = 16, /* DSI_PLL_REGN */  //Fint 2.4 MHz
 
   .regm  =120, /* DSI_PLL_REGM */ // DDR Clock 576MHZ  One Lane speed  = 288MHZ
 
   .regm_dispc =4, /* PLL_CLK1 (M4) *///PLL1 144MHz   
   .regm_dsi = 4, /* PLL_CLK2 (M5) *///PLL2 144MHz
 
   .lp_clk_div = 10, /* LPDIV */ // LP 7.2MHz
 
 
   .dsi_fclk_src   = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,
  },
 },
 .channel  = OMAP_DSS_CHANNEL_LCD,
 .skip_init = false,
 .platform_enable = NULL,
 .platform_disable = NULL,
   
};

 

 

static struct panel_config panel_configs[] = {
 {
  .name  = "ili9486_dsi",
  .type  = 0,
  .timings = {
   .x_res  = 320,
   .y_res  = 480,
   .pixel_clock = 10000, 

   .hsw  =3,
   .hfp  = 16,
   .hbp  = 20,
   .vsw  = 2,
   .vfp  = 8,
   .vbp  = 12,
  },
  .sleep  = {
   .sleep_in = 5,
   .sleep_out = 5,
   .hw_reset = 100,
   .enable_te = 100, 

  },
  .reset_sequence = {
   .high  = 10,
   .low  = 10,
  },
 },
};

 

 

thanks your support.

  • Hi William,

    Could you please let me know which software release you are using currently? Is this a custom panda board based on OMAP4460 with ILI9486 panel?

    Thanks & Best Regards,

    Venkat

  • Hi William,

    Could you also share outputs for the following sysfs commands?


    cat /sys/kernel/debug/omapdss/clk

    cat /sys/kernel/debug/omapdss/dispc

    cat /sys/kernel/debug/omapdss/dsi1_regs

    cat /sys/kernel/debug/omapdss/dss

    Thanks & Best Regards,

    Venkat

  • Hi Venkat

     

    We have use Linaro 12.04 Pandaboard release build.

    The develop platform is PandaBoard ES (OMAP 4460).

    reference driver is panel-taal.c.

  • Dear Venkat

     

    Here is my sysfs output

     

    =================sys/kernel/debug/omapdss/clk =========================         
    - DSS -
    dpll4_ck 1536000000
    DSS_FCK (DSS_FCLK) = 1536000000 / 9  = 170666666
    - DISPC -
    dispc fclk source = DSS_FCK (DSS_FCLK)
    fck  170666666      
    - DISPC-CORE-CLK -
    lck  170666666       lck div 1
    - LCD1 -
    lcd1_clk source = DSI_PLL_HSDIV_DISPC (PLL1_CLK1)
    lck  144000000       lck div 1
    pck  10285714        pck div 14
    - LCD2 -
    lcd2_clk source = DSS_FCK (DSS_FCLK)
    lck  42666666        lck div 4
    pck  42666666        pck div 1
    - DSI1 PLL -
    dsi pll source = dss_sys_clk
    Fint  2400000         regn 16
    CLKIN4DDR 576000000       regm 120
    DSS_FCK (DSS_FCLK) 144000000       regm_dispc 4 (off)
    DSI_PLL_HSDIV_DSI (PLL1_CLK2) 144000000       regm_dsi 4 (on)
    - DSI1 -
    dsi fclk source = DSI_PLL_HSDIV_DSI (PLL1_CLK2)
    DSI_FCLK 144000000
    DDR_CLK  144000000
    TxByteClkHS 36000000
    LP_CLK  7200000

     

    ===============================sys/kernel/debug/omapdss/dispc  =======================

                        
    DISPC_REVISION                                     00000040
    DISPC_SYSCONFIG                                    00002015
    DISPC_SYSSTATUS                                    00000001
    DISPC_IRQSTATUS                                    000000a2
    DISPC_IRQENABLE                                    0012d640
    DISPC_CONTROL                                      00018209
    DISPC_CONFIG                                       00020004
    DISPC_CAPABLE                                      00000000
    DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD)          00000000
    DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT)        00000000
    DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD)            00000000
    DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT)          00000000
    DISPC_LINE_STATUS                                  0000000a
    DISPC_LINE_NUMBER                                  00000000
    DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD)               01300f02
    DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD)               00c00801
    DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD)               00000000
    DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD)               0001000e
    DISPC_GLOBAL_ALPHA                                 ffffffff
    DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT)             00000000
    DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD)               01df013f
    DISPC_CONTROL2                                     00000000
    DISPC_CONFIG2                                      00000000
    DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2)         00000000
    DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2)           00000000
    DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD2)              00000000
    DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD2)              00000000
    DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD2)              00000000
    DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD2)              00040001
    DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD2)              00000000
    DISPC_OVL_BA0(OMAP_DSS_GFX)                        bd000000
    DISPC_OVL_BA1(OMAP_DSS_GFX)                        bd000000
    DISPC_OVL_POSITION(OMAP_DSS_GFX)                   00000000
    DISPC_OVL_SIZE(OMAP_DSS_GFX)                       01df013f
    DISPC_OVL_ATTRIBUTES(OMAP_DSS_GFX)                 020000ad
    DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_GFX)             04ff0098
    DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_GFX)           00000500
    DISPC_OVL_ROW_INC(OMAP_DSS_GFX)                    00000001
    DISPC_OVL_PIXEL_INC(OMAP_DSS_GFX)                  00000001
    DISPC_OVL_WINDOW_SKIP(OMAP_DSS_GFX)                00000000
    DISPC_OVL_TABLE_BA(OMAP_DSS_GFX)                   00000000
    DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD)            00000000
    DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD)            00000000
    DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD)            00000000
    DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD)             00000000
    DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD)             00000000
    DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD)             00000000
    DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2)           00000000
    DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2)           00000000
    DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2)           00000000
    DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2)            00000000
    DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2)            00000000
    DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2)            00000000
    DISPC_OVL_PRELOAD(OMAP_DSS_GFX)                    000004ff
    DISPC_OVL_BA0(o)                                   00000000
    DISPC_OVL_BA1(o)                                   00000000
    DISPC_OVL_POSITION(o)                              00000000
    DISPC_OVL_SIZE(o)                                  00000000
    DISPC_OVL_ATTRIBUTES(o)                            00008400
    DISPC_OVL_FIFO_THRESHOLD(o)                        07ff07f8
    DISPC_OVL_FIFO_SIZE_STATUS(o)                      00000800
    DISPC_OVL_ROW_INC(o)                               00000001
    DISPC_OVL_PIXEL_INC(o)                             00000001
    DISPC_OVL_FIR(o)                                   04000400
    DISPC_OVL_PICTURE_SIZE(o)                          00000000
    DISPC_OVL_ACCU0(o)                                 00000000
    DISPC_OVL_ACCU1(o)                                 00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_BA0_UV(o)                                00000000
    DISPC_OVL_BA1_UV(o)                                00000000
    DISPC_OVL_FIR2(o)                                  04000400
    DISPC_OVL_ACCU2_0(o)                               00000000
    DISPC_OVL_ACCU2_1(o)                               00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_ATTRIBUTES2(o)                           00000000
    DISPC_OVL_PRELOAD(o)                               00000100
    DISPC_OVL_BA0(o)                                   00000000
    DISPC_OVL_BA1(o)                                   00000000
    DISPC_OVL_POSITION(o)                              00000000
    DISPC_OVL_SIZE(o)                                  00000000
    DISPC_OVL_ATTRIBUTES(o)                            00008400
    DISPC_OVL_FIFO_THRESHOLD(o)                        07ff07f8
    DISPC_OVL_FIFO_SIZE_STATUS(o)                      00000800
    DISPC_OVL_ROW_INC(o)                               00000001
    DISPC_OVL_PIXEL_INC(o)                             00000001
    DISPC_OVL_FIR(o)                                   04000400
    DISPC_OVL_PICTURE_SIZE(o)                          00000000
    DISPC_OVL_ACCU0(o)                                 00000000
    DISPC_OVL_ACCU1(o)                                 00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_BA0_UV(o)                                00000000
    DISPC_OVL_BA1_UV(o)                                00000000
    DISPC_OVL_FIR2(o)                                  04000400
    DISPC_OVL_ACCU2_0(o)                               00000000
    DISPC_OVL_ACCU2_1(o)                               00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_ATTRIBUTES2(o)                           00000000
    DISPC_OVL_PRELOAD(o)                               00000100
    DISPC_OVL_BA0(o)                                   00000000
    DISPC_OVL_BA1(o)                                   00000000
    DISPC_OVL_POSITION(o)                              00000000
    DISPC_OVL_SIZE(o)                                  00000000
    DISPC_OVL_ATTRIBUTES(o)                            00008400
    DISPC_OVL_FIFO_THRESHOLD(o)                        07ff07f8
    DISPC_OVL_FIFO_SIZE_STATUS(o)                      00000800
    DISPC_OVL_ROW_INC(o)                               00000001
    DISPC_OVL_PIXEL_INC(o)                             00000001
    DISPC_OVL_FIR(o)                                   04000400
    DISPC_OVL_PICTURE_SIZE(o)                          00000000
    DISPC_OVL_ACCU0(o)                                 00000000
    DISPC_OVL_ACCU1(o)                                 00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_BA0_UV(o)                                00000000
    DISPC_OVL_BA1_UV(o)                                00000000
    DISPC_OVL_FIR2(o)                                  04000400
    DISPC_OVL_ACCU2_0(o)                               00000000
    DISPC_OVL_ACCU2_1(o)                               00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_ATTRIBUTES2(o)                           00000000
    DISPC_OVL_PRELOAD(o)                               00000100

    ===============kernel/debug/omapdss/dsi1_regs   ====================================

    DSI_REVISION                        00000030
    DSI_SYSCONFIG                       00000011
    DSI_SYSSTATUS                       00000001
    DSI_IRQSTATUS                       000000a0
    DSI_IRQENABLE                       0015c000
    DSI_CTRL                            00eaea59
    DSI_COMPLEXIO_CFG1                  6a000021
    DSI_COMPLEXIO_IRQ_STATUS            00000000
    DSI_COMPLEXIO_IRQ_ENABLE            3ff07fff
    DSI_CLK_CTRL                        a034600a
    DSI_TIMING1                         7fff7fff
    DSI_TIMING2                         ffff7fff
    DSI_VM_TIMING1                      ff02c03e
    DSI_VM_TIMING2                      0402080c
    DSI_VM_TIMING3                      043401e0
    DSI_CLK_TIMING                      00001311
    DSI_TX_FIFO_VC_SIZE                 13121110
    DSI_RX_FIFO_VC_SIZE                 13121110
    DSI_COMPLEXIO_CFG2                  00030000
    DSI_RX_FIFO_VC_FULLNESS             00000000
    DSI_VM_TIMING4                      00487296
    DSI_TX_FIFO_VC_EMPTINESS            1f1f1f1f
    DSI_VM_TIMING5                      0082df3b
    DSI_VM_TIMING6                      7a6731d1
    DSI_VM_TIMING7                      0012000f
    DSI_STOPCLK_TIMING                  00000080
    DSI_VC_CTRL(0)                      20808f91
    DSI_VC_TE(0)                        00000000
    DSI_VC_LONG_PACKET_HEADER(0)        00000000
    DSI_VC_LONG_PACKET_PAYLOAD(0)       00000000
    DSI_VC_SHORT_PACKET_HEADER(0)       00000000
    DSI_VC_IRQSTATUS(0)                 00000004
    DSI_VC_IRQENABLE(0)                 000000db
    DSI_VC_CTRL(1)                      20808f81
    DSI_VC_TE(1)                        00000000
    DSI_VC_LONG_PACKET_HEADER(1)        00000000
    DSI_VC_LONG_PACKET_PAYLOAD(1)       00000000
    DSI_VC_SHORT_PACKET_HEADER(1)       00000000
    DSI_VC_IRQSTATUS(1)                 00000000
    DSI_VC_IRQENABLE(1)                 000000db
    DSI_VC_CTRL(2)                      20808d81
    DSI_VC_TE(2)                        00000000
    DSI_VC_LONG_PACKET_HEADER(2)        00000000
    DSI_VC_LONG_PACKET_PAYLOAD(2)       00000000
    DSI_VC_SHORT_PACKET_HEADER(2)       00000000
    DSI_VC_IRQSTATUS(2)                 00000000
    DSI_VC_IRQENABLE(2)                 000000db
    DSI_VC_CTRL(3)                      20808d81
    DSI_VC_TE(3)                        00000000
    DSI_VC_LONG_PACKET_HEADER(3)        00000000
    DSI_VC_LONG_PACKET_PAYLOAD(3)       00000000
    DSI_VC_SHORT_PACKET_HEADER(3)       00000000
    DSI_VC_IRQSTATUS(3)                 00000000
    DSI_VC_IRQENABLE(3)                 000000db
    DSI_DSIPHY_CFG0                     0d1c0e15
    DSI_DSIPHY_CFG1                     42040b26
    DSI_DSIPHY_CFG2                     b800000a
    DSI_DSIPHY_CFG5                     e3000000
    DSI_PLL_CONTROL                     00000000
    DSI_PLL_STATUS                      00000383
    DSI_PLL_GO                          00000000
    DSI_PLL_CONFIGURATION1              0c60f01f
    DSI_PLL_CONFIGURATION2              00656008


    ===========sys/kernel/debug/omapdss/dss ======================
                           
    DSS_REVISION                        00000040
    DSS_SYSCONFIG                       00000000
    DSS_SYSSTATUS                       00000001
    DSS_CONTROL                         00000003

  • Hi Venkat

    We have used 0x2E  RGB666  24bit loosely format to panel (raise one lane speed to 350MHZ), have shown frame on panel.

    But color have some mistake.

    The loosely packet format on ILI9486  

    (bit 6 7 be ignored) 

    |0      5|67|0      5|67|0      5|67|

    |----R--|---|----G--|---|----B--|---|

     

    The loosely packet format on OMAP4460

    (bit 0 1 be ignored) 

    |01|2      7|01|2      7|01|2      7|

    |---|--R----|---|--G----|---|--B----|

     

    Could we modify the bit format from OMAP4460??

    thank you.

    Data Type One Lane Speed
    0x0E RGB 565 16bit 240MHZ
    0x1E RGB 666 18bit packed 270MHZ
    0x2E RGB 666 24bit loosely 350MHZ
    0x3E RGB 888 24bit 350MHZ

  • Hi William,

    You can modify the bit format for OMAP4460 by programming the Format field of DISPC_GFX_ATTRIBUTES to select one of the supported formats mentioned below as per the OMAP4460 TRM. Please check if you are setting the format correctly to 0x9: RGB24-888 (24-bit container).

    4:1 FORMAT Graphics format. RW 0x0
    It defines the pixel format when fetching the graphics
    picture into memory.
    0x6: RGB16-565
    0x1: BITMAP2 (CLUT is required to be used)
    0xA: RGBx12-4444
    0x7: ARGB16-1555
    0xD: RGBA32-8888
    0x0: BITMAP1 (CLUT is required to be used)
    0x2: BITMAP4 (CLUT is required to be used)
    0x8: xRGB24-8888 (32-bit container)
    0x9: RGB24-888 (24-bit container)
    0xB: RGBA12-4444
    0x4: xRGB12-4444
    0x5: ARGB16-4444
    0xF: xRGB15-1555
    0xC: ARGB32-8888
    0x3: BITMAP8 (CLUT is required to be used)
    0xE: RGBx24-8888 (24-bit RGB aligned on MSB of the
    32-bit container)

    I will look over the other inputs from you and provide further comments later.

    Thanks & Best Regards,

    Venkat

  • Dear Venkat

    thansk your support.

    I found a strage things when we set "dssdev->ctrl.pixel_size = 24;"

    The DISPC_GFX_ATTRIBUTES register will set 0xc not ox9 ; // 0xC: ARGB32-8888

    If we modify the value , m = 0x9

      case OMAP_DSS_COLOR_RGB24P:
       m = 0x9; break;

    the frame will show but not correct (seems like two image , right and left frame overlay )

    shall we need to set pixel size on another place??

    thank you.

  • Does REGN and REGM have any restriction??

    We have modify these value to output 16 bit pixel data from pandaboard ( data lane speed 240MHZ ).

    DSI output is 0x0e (16 bit pixel)

    ctrl.pixel_size = 16;

    CASE 1: Have frame but not correct . seems like lane speed too slow (all black but have some image flick on panel).

    clocks = {
      .dispc = {
       .channel = {

        .lck_div = 1, /* LCD */// Logic clk 120MHz

                                    .pck_div = 10, /* PCD */ //12MHz
     
        .lcd_clk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
       },
       .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK,
      },

      .dsi = {

       .regn  = 16, /* DSI_PLL_REGN */  //Fint 2.4 MHz

       .regm  =100, /* DSI_PLL_REGM */ // DDR clock 480MHZ   One Lane speed 480 / 2 = 240MHZ

     
       .regm_dispc =4, /* PLL_CLK1 (M4) *///PLL1 120MHz
     
       .regm_dsi = 4, /* PLL_CLK2 (M5) *///PLL2 120MHz

     
       .lp_clk_div = 10, /* LPDIV */ 
     
     
       .dsi_fclk_src   = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,
      },
     },

    CASE 2 : no frame on panel.

    .clocks = {
      .dispc = {
       .channel = {

        .lck_div = 1, /* LCD */// Logic clk 132MHz

                                    .pck_div = 11, /* PCD */ //12MHz
     
        .lcd_clk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
       },
       .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK,
      },

      .dsi = {

       .regn  = 16, /* DSI_PLL_REGN */  //Fint 2.4 MHz

       .regm  =110, /* DSI_PLL_REGM */ // DDR clock 528MHZ   One Lane speed 528 / 2 = 264MHZ

     
       .regm_dispc =4, /* PLL_CLK1 (M4) *///PLL1 132MHz
     
       .regm_dsi = 4, /* PLL_CLK2 (M5) *///PLL2 132MHz

     
       .lp_clk_div = 10, /* LPDIV */
     
     
       .dsi_fclk_src   = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,
      },
     },

  • Hi William,

    Seems like an issue related to DSI and DISPC configuration parameters tuning. Let me look at it further in detail and see if the issue is due to some mismatch between DSI and DISPC clocks?

    I will give you further update after some more analysis of your current parameters.

    Thanks & Best Regards,

    Venkat

  • Dear Venkat

    We have use these parameter.

    the pixel clock is 12MHZ , the frequency have been modfiy from 10MHZ to 15MHZ

    But haven't any change there.

    Could you give us some support about this situation??

    thank you.

     

    ILI9486 SPEC

    Data Type One Lane Speed
    0x0E RGB 565 16bit 240MHZ

    clocks = {

      .dispc = {
       .channel = {

        .lck_div = 1, /* LCD */// Logic clk 120MHz

        .pck_div = 10, /* PCD */ //12MHz 
     
        .lcd_clk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
       },
       .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK,
      },

      .dsi = {

       .regn  = 16, /* DSI_PLL_REGN */  //Fint 2.4 MHz

       .regm  =100, /* DSI_PLL_REGM */ // DDR clock 480MHZ   One Lane speed 480 / 2 = 240MHZ

     
       .regm_dispc =4, /* PLL_CLK1 (M4) *///PLL1 120MHz 
     
       .regm_dsi = 4, /* PLL_CLK2 (M5) *///PLL2 120MHz

     
       .lp_clk_div = 10, /* LPDIV */ 
     
     
       .dsi_fclk_src   = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,
      },
     },

    #Display On Panel

    #Original frame

  • Hi Wu William

    Could you please try this configuration?

    .clocks = {
     .dispc = {
     .channel = {
     .lck_div = 1,
     .pck_div = 18,
     .lcd_clk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
     },
     .dispc_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
     },

    .dsi = {
     .regn = 24,
     .regm = 174,
     .regm_dispc = 2,
     .regm_dsi = 2,
     .lp_clk_div = 9,
     .offset_ddr_clk = 0,
     .dsi_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,
     },
     },

    .panel = {
     .timings = {
     .x_res = 320,
     .y_res = 480,
     .pixel_clock = 9898,
     .hfp = 11,
     .hsw = 3,
     .hbp = 2,
     .vfp = 7,
     .vsw = 2,
     .vbp = 2,
     },
     },

    .ctrl = {
     .pixel_size = 16,
     },

    For now, leave the DISPC_GFX_ATTRIBUTES color mode on its original state.

    Please post a Register Dump with this configuration.

    If this still fails, please disable the GFX overlay and set the default color to a known color, Red or Blue.

    Regards.

    Rafael

  • Dear Rodriguez

    Still not work on these settings

    omapdss DSI error: DSI CIO error, cio irqstatus 800000.


    And we can't echo 0 > /sys/devices/platform/omapdss/display2/enabled

    Is our display driver function not ready(if yes which function shall we implement)?

    thanks your support.

    ================= cat d/omapdss/dsi1_regs ======================= 
    DSI_REVISION 00000030
    DSI_SYSCONFIG 00000011
    DSI_SYSSTATUS 00000001
    DSI_IRQSTATUS 00000020
    DSI_IRQENABLE 0015c000
    DSI_CTRL 00eaea19
    DSI_COMPLEXIO_CFG1 6a000021
    DSI_COMPLEXIO_IRQ_STATUS 00000000
    DSI_COMPLEXIO_IRQ_ENABLE 3ff07fff
    DSI_CLK_CTRL a0346009
    DSI_TIMING1 7fff7fff
    DSI_TIMING2 ffff7fff
    DSI_VM_TIMING1 ff003015
    DSI_VM_TIMING2 04070202
    DSI_VM_TIMING3 029f01e0
    DSI_CLK_TIMING 00001311
    DSI_TX_FIFO_VC_SIZE 13121110
    DSI_RX_FIFO_VC_SIZE 13121110
    DSI_COMPLEXIO_CFG2 00030000
    DSI_RX_FIFO_VC_FULLNESS 00000000
    DSI_VM_TIMING4 00487296
    DSI_TX_FIFO_VC_EMPTINESS 1f1f1f1f
    DSI_VM_TIMING5 0082df3b
    DSI_VM_TIMING6 7a6731d1
    DSI_VM_TIMING7 0012000f
    DSI_STOPCLK_TIMING 00000080
    DSI_VC_CTRL(0) 20808f91
    DSI_VC_TE(0) 00000000
    DSI_VC_LONG_PACKET_HEADER(0) 00000000
    DSI_VC_LONG_PACKET_PAYLOAD(0) 00000000
    DSI_VC_SHORT_PACKET_HEADER(0) 00000000
    DSI_VC_IRQSTATUS(0) 00000004
    DSI_VC_IRQENABLE(0) 000000db
    DSI_VC_CTRL(1) 20808f81
    DSI_VC_TE(1) 00000000
    DSI_VC_LONG_PACKET_HEADER(1) 00000000
    DSI_VC_LONG_PACKET_PAYLOAD(1) 00000000
    DSI_VC_SHORT_PACKET_HEADER(1) 00000000
    DSI_VC_IRQSTATUS(1) 00000000
    DSI_VC_IRQENABLE(1) 000000db
    DSI_VC_CTRL(2) 20808d81
    DSI_VC_TE(2) 00000000
    DSI_VC_LONG_PACKET_HEADER(2) 00000000
    DSI_VC_LONG_PACKET_PAYLOAD(2) 00000000
    DSI_VC_SHORT_PACKET_HEADER(2) 00000000
    DSI_VC_IRQSTATUS(2) 00000000
    DSI_VC_IRQENABLE(2) 000000db
    DSI_VC_CTRL(3) 20808d81
    DSI_VC_TE(3) 00000000
    DSI_VC_LONG_PACKET_HEADER(3) 00000000
    DSI_VC_LONG_PACKET_PAYLOAD(3) 00000000
    DSI_VC_SHORT_PACKET_HEADER(3) 00000000
    DSI_VC_IRQSTATUS(3) 00000000
    DSI_VC_IRQENABLE(3) 000000db
    DSI_DSIPHY_CFG0 0c1b0e15
    DSI_DSIPHY_CFG1 42040b25
    DSI_DSIPHY_CFG2 b800000a
    DSI_DSIPHY_CFG5 e3000000
    DSI_PLL_CONTROL 00000000
    DSI_PLL_STATUS 00000383
    DSI_PLL_GO 00000000
    DSI_PLL_CONFIGURATION1 04215c2f
    DSI_PLL_CONFIGURATION2 00656008


    ====================== cat d/omapdss/dispc ============================= 
    DISPC_REVISION 00000040
    DISPC_SYSCONFIG 00002015
    DISPC_SYSSTATUS 00000001
    DISPC_IRQSTATUS 00000082
    DISPC_IRQENABLE 0012d640
    DISPC_CONTROL 00018109
    DISPC_CONFIG 00020004
    DISPC_CAPABLE 00000000
    DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD) 00000000
    DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT) 00000000
    DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD) 00000000
    DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT) 00000000
    DISPC_LINE_STATUS 000000c1
    DISPC_LINE_NUMBER 00000000
    DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD) 0010020a
    DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD) 00200206
    DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD) 00000000
    DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD) 00010012
    DISPC_GLOBAL_ALPHA ffffffff
    DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT) 00000000
    DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD) 01df013f
    DISPC_CONTROL2 00000000
    DISPC_CONFIG2 00000000
    DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2) 00000000
    DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2) 00000000
    DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD2) 00000000
    DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD2) 00000000
    DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD2) 00000000
    DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD2) 00040001
    DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD2) 00000000
    DISPC_OVL_BA0(OMAP_DSS_GFX) bd000000
    DISPC_OVL_BA1(OMAP_DSS_GFX) bd000000
    DISPC_OVL_POSITION(OMAP_DSS_GFX) 00000000
    DISPC_OVL_SIZE(OMAP_DSS_GFX) 01df013f
    DISPC_OVL_ATTRIBUTES(OMAP_DSS_GFX) 0200008d
    DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_GFX) 04ff0098
    DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_GFX) 00000500
    DISPC_OVL_ROW_INC(OMAP_DSS_GFX) 00000001
    DISPC_OVL_PIXEL_INC(OMAP_DSS_GFX) 00000001
    DISPC_OVL_WINDOW_SKIP(OMAP_DSS_GFX) 00000000
    DISPC_OVL_TABLE_BA(OMAP_DSS_GFX) 00000000
    DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD) 00000000
    DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD) 00000000
    DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD) 00000000
    DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD) 00000000
    DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD) 00000000
    DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD) 00000000
    DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2) 00000000
    DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2) 00000000
    DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2) 00000000
    DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2) 00000000
    DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2) 00000000
    DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2) 00000000
    DISPC_OVL_PRELOAD(OMAP_DSS_GFX) 000004ff
    DISPC_OVL_BA0(o) 00000000
    DISPC_OVL_BA1(o) 00000000
    DISPC_OVL_POSITION(o) 00000000
    DISPC_OVL_SIZE(o) 00000000
    DISPC_OVL_ATTRIBUTES(o) 00008400
    DISPC_OVL_FIFO_THRESHOLD(o) 07ff07f8
    DISPC_OVL_FIFO_SIZE_STATUS(o) 00000800
    DISPC_OVL_ROW_INC(o) 00000001
    DISPC_OVL_PIXEL_INC(o) 00000001
    DISPC_OVL_FIR(o) 04000400
    DISPC_OVL_PICTURE_SIZE(o) 00000000
    DISPC_OVL_ACCU0(o) 00000000
    DISPC_OVL_ACCU1(o) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_BA0_UV(o) 00000000
    DISPC_OVL_BA1_UV(o) 00000000
    DISPC_OVL_FIR2(o) 04000400
    DISPC_OVL_ACCU2_0(o) 00000000
    DISPC_OVL_ACCU2_1(o) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_ATTRIBUTES2(o) 00000000
    DISPC_OVL_PRELOAD(o) 00000100
    DISPC_OVL_BA0(o) 00000000
    DISPC_OVL_BA1(o) 00000000
    DISPC_OVL_POSITION(o) 00000000
    DISPC_OVL_SIZE(o) 00000000
    DISPC_OVL_ATTRIBUTES(o) 00008400
    DISPC_OVL_FIFO_THRESHOLD(o) 07ff07f8
    DISPC_OVL_FIFO_SIZE_STATUS(o) 00000800
    DISPC_OVL_ROW_INC(o) 00000001
    DISPC_OVL_PIXEL_INC(o) 00000001
    DISPC_OVL_FIR(o) 04000400
    DISPC_OVL_PICTURE_SIZE(o) 00000000
    DISPC_OVL_ACCU0(o) 00000000
    DISPC_OVL_ACCU1(o) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_BA0_UV(o) 00000000
    DISPC_OVL_BA1_UV(o) 00000000
    DISPC_OVL_FIR2(o) 04000400
    DISPC_OVL_ACCU2_0(o) 00000000
    DISPC_OVL_ACCU2_1(o) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_ATTRIBUTES2(o) 00000000
    DISPC_OVL_PRELOAD(o) 00000100
    DISPC_OVL_BA0(o) 00000000
    DISPC_OVL_BA1(o) 00000000
    DISPC_OVL_POSITION(o) 00000000
    DISPC_OVL_SIZE(o) 00000000
    DISPC_OVL_ATTRIBUTES(o) 00008400
    DISPC_OVL_FIFO_THRESHOLD(o) 07ff07f8
    DISPC_OVL_FIFO_SIZE_STATUS(o) 00000800
    DISPC_OVL_ROW_INC(o) 00000001
    DISPC_OVL_PIXEL_INC(o) 00000001
    DISPC_OVL_FIR(o) 04000400
    DISPC_OVL_PICTURE_SIZE(o) 00000000
    DISPC_OVL_ACCU0(o) 00000000
    DISPC_OVL_ACCU1(o) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_BA0_UV(o) 00000000
    DISPC_OVL_BA1_UV(o) 00000000
    DISPC_OVL_FIR2(o) 04000400
    DISPC_OVL_ACCU2_0(o) 00000000
    DISPC_OVL_ACCU2_1(o) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_ATTRIBUTES2(o) 00000000
    DISPC_OVL_PRELOAD(o) 00000100


    ============== cat d/omapdss/clk ================== 
    - DSS -
    dpll4_ck 1536000000
    DSS_FCK (DSS_FCLK) = 1536000000 / 9 = 170666666
    - DISPC -
    dispc fclk source = DSS_FCK (DSS_FCLK)
    fck 170666666
    - DISPC-CORE-CLK -
    lck 170666666 lck div 1
    - LCD1 -
    lcd1_clk source = DSI_PLL_HSDIV_DISPC (PLL1_CLK1)
    lck 278400000 lck div 1
    pck 15466666 pck div 18
    - LCD2 -
    lcd2_clk source = DSS_FCK (DSS_FCLK)
    lck 42666666 lck div 4
    pck 42666666 pck div 1
    - DSI1 PLL -
    dsi pll source = dss_sys_clk
    Fint 1600000 regn 24
    CLKIN4DDR 556800000 regm 174
    DSS_FCK (DSS_FCLK) 278400000 regm_dispc 2 (off)
    DSI_PLL_HSDIV_DSI (PLL1_CLK2) 278400000 regm_dsi 2 (on)
    - DSI1 -
    dsi fclk source = DSI_PLL_HSDIV_DSI (PLL1_CLK2)
    DSI_FCLK 278400000
    DDR_CLK 139200000
    TxByteClkHS 34800000
    LP_CLK 15466666

  • Dear Rodriguez

    Is this error will be caused by "DSI_PLL_HSDIV_DSI (PLL1_CLK2) 278400000 regm_dsi " is bigger than 180M??

     

     

  • Hi Wu

    My apologies for the late reply, You are right. It is bigger than 180M.
    Sorry about that. Let me start over, now with your previous timing calculations. Please correct me if I am wrong.
    Here is what you had:
    • Width: 320
    • Height: 480
    • Refresh Rate: 60Hz
    • Pixel Format: 16 bit (RGB565)
    • Automatic Update Panel (Video Mode)
    • DISPC blankings:
    • hfp: 16   hbp: 20   hsw: 3
    • vfp: 8   vbp: 12 vsw: 2
    • SYS_CLK = 38.4 MHz
    • LCD1 = 1
    • PCD1 = 10
    • REGN  = 16
    • REGM = 100
    • M4REG = 4
    • M5REG = 4

    So from this we have:

    Pixel Clock
    = (Width+hfp+hbp+hsw)*(Height+vfp+vbp+vsw)*refresh_rate
    =(320+16+20+3) * (480+8+12+2)*60 = 10.813 MHz

    So our target LCD1_PCLK should be the same. We can play with the blankings, REGM and REGN and M4REG to approach this.

    CLKIN4DDR
    =(2*SYS_CLK*REGM)/(REGN+1)
    =(2*38.4MHz*100)/(16+1)=451.765MHz
    PLL1_CLK1
    =CLKIN4DDR / (M4REG+1)
    =451.765MHz / (4+1) = 90.353 MHz
    LCD1_PCLK
    =PLL1CLK / (LCD1 * PCD1)
    =90.353MHz / (1*10) = 9.035 MHz
    Which is a lot smaller than our target pixel clock of 10.813 MHz, like you said.
    Let's try the following changes:
    • DISPC blankings:
    • hfp: 10   hbp: 3   hsw: 4
    • vfp: 43   vbp: 2 vsw: 2
    • SYS_CLK = 38.4 MHz
    • LCD1 = 1
    • PCD1 = 16
    • REGN  = 24
    • REGM = 111
    • M4REG = 1
    • M5REG = 1
    With these we have:
    Pixel Clock
    = (Width+hfp+hbp+hsw)*(Height+vfp+vbp+vsw)*refresh_rate
    =(320+10+3+4) * (480+43+2+2)*60 = 10.656MHz
    CLKIN4DDR
    =(2*SYS_CLK*REGM)/(REGN+1)
    =(2*38.4MHz*111)/(24+1)= 340.992 MHz
    PLL1_CLK1
    =CLKIN4DDR / (M4REG+1)
    =340.992MHz / (1+1) = 170.496MHz
    LCD1_PCLK
    =PLL1CLK / (LCD1 * PCD1)
    =170.496MHz / (1*16) = 10.656 MHz
    Which is exactly our target Pixel Clock.
    Could you try this, please?
           .clocks = {
                 .dispc = {
                         .channel = {
                               .lck_div        = 1,
                               .pck_div        = 16,
                               .lcd_clk_src    = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
                        },
                        .dispc_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
                 },

     

                 .dsi = {
                        .regn           = 24,
                        .regm           = 111,
                        .regm_dispc     = 1,
                        .regm_dsi       = 1,
                        .lp_clk_div     = 9,
                        .offset_ddr_clk = 0,
                        .dsi_fclk_src   = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,
                 },
           },

     

           .panel = {
                 .timings = {
                        .x_res       = 320,
                        .y_res       = 480,
                        .pixel_clock = 10656,
                        .hfp         = 10,
                               .hsw         = 4,
                        .hbp         = 3,
                        .vfp         = 43,
                        .vsw         = 2,
                        .vbp         = 2,
                 },
           },

     

           .ctrl = {
                 .pixel_size = 16,
           },
    Regards
    Rafael
  • Dear Rodriguez

     

    thanks your support.

    But we got some error here.

    omapdss DSI error: DSI CIO error, cio irqstatus c00000         

    omapdss DSI error: DSI CIO error, cio irqstatus 800000   

     

    And I have some confuse about that calculate frequency.

    Pixel Clock : We have the same formula
    = (Width+hfp+hbp+hsw)*(Height+vfp+vbp+vsw)*refresh_rate
    =(320+10+3+4) * (480+43+2+2)*60 = 10.656MHz
     
    CLKIN4DDR : some different , (2*SYS_CLK*REGM)/(REGN) = 355.2 MHZ
    =(2*SYS_CLK*REGM)/(REGN+1)
    =(2*38.4MHz*111)/(24+1)= 340.992 MHz
    PLL1_CLK1 : CLKIN4DDR / (M4REG) = 355.2 MHZ
    =CLKIN4DDR / (M4REG+1)
    =340.992MHz / (1+1) = 170.496MHz
    LCD1_PCLK : the same formula.
    =PLL1CLK / (LCD1 * PCD1)
    =170.496MHz / (1*16) = 10.656 MHz
     
     
    Kernel output message calculte frequency below.
     
    [    5.588806] omapdss DSI: DSI Fint 1600000                                  
    [    5.597625] omapdss DSI: clkin (dss_sys_clk) rate 38400000, highfreq 0     
    [    5.597625] omapdss DSI: CLKIN4DDR = 2 * 111 / 24 * 38400000 / 1 = 355200000
    [    5.608734] omapdss DSI: Data rate on 1 DSI lane 177 Mbps                  
    [    5.608734] omapdss DSI: Clock lane freq 88800000 Hz                       
    [    5.627075] omapdss DSI: regm_dispc = 1, DSI_PLL_HSDIV_DISPC (PLL1_CLK1) = 0
    [    5.627075] omapdss DSI: regm_dsi = 1, DSI_PLL_HSDIV_DSI (PLL1_CLK2) = 35520
    [    5.643127] omapdss DSI: PLL config done                                   
    [    5.647399] omapdss DSI: PLL OK                                            
    [    5.647399] omapdss DISPC: lck = 355200000 (1)                             
    [    5.650726] omapdss DISPC: pck = 22200000 (16)      
     
     
  • You are right !! I gave you the register value for M4REG, M5REG and REGN

    Sorry.

    Try this, it gives me the correct clock values we calculated:

           .clocks = {
                 .dispc = {
                         .channel = {
                               .lck_div        = 1,
                               .pck_div        = 16,
                               .lcd_clk_src    = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
                        },
                        .dispc_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
                 },

     

                 .dsi = {
                        .regn           = 25,
                        .regm           = 111,
                        .regm_dispc     = 2,
                        .regm_dsi       = 2,
                        .lp_clk_div     = 9,
                        .offset_ddr_clk = 0,
                        .dsi_fclk_src   = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,
                 },
           },

     

           .panel = {
                 .timings = {
                        .x_res       = 320,
                        .y_res       = 480,
                        .pixel_clock = 10656,
                        .hfp         = 10,
                               .hsw         = 4,
                        .hbp         = 3,
                        .vfp         = 43,
                        .vsw         = 2,
                        .vbp         = 2,
                 },
           },

     

           .ctrl = {
                 .pixel_size = 16,
           },

    Check the register DSI_PLL_CONFIGURATION1, you should have

    DSI_PLL_CONFIGURATION1              0420de31 
    That is:
       0     00001          00001          000001101111           00011000   1
             M5REG=1        M4REG=1        REGM = 111                REGN = 24          
    This is what I recommended on the previous post. I forgot to add 1 to M5REG, M4REG and REGN.

    You should get this clock dump

    - DSS -
    dpll4_ck 1536000000
    DSS_FCK (DSS_FCLK) = 1536000000 / 9 = 170666666
    - DISPC -
    dispc fclk source = DSI_PLL_HSDIV_DISPC (PLL1_CLK1)
    fck 170496000
    - DISPC-CORE-CLK -
    lck 170496000 lck div 1
    - LCD1 -
    lcd1_clk source = DSI_PLL_HSDIV_DISPC (PLL1_CLK1)
    lck 170496000 lck div 1
    pck 10656000 pck div 16
    - LCD2 -
    lcd2_clk source = DSS_FCK (DSS_FCLK)
    lck 42666666 lck div 4
    pck 42666666 pck div 1
    - DSI1 PLL -
    dsi pll source = dss_sys_clk
    Fint 1536000 regn 25
    CLKIN4DDR 340992000 regm 111
    DSI_PLL_HSDIV_DISPC (PLL1_CLK1) 170496000 regm_dispc 2 (on)
    DSI_PLL_HSDIV_DSI (PLL1_CLK2) 170496000 regm_dsi 2 (on)
    - DSI1 -
    dsi fclk source = DSI_PLL_HSDIV_DSI (PLL1_CLK2)
    DSI_FCLK 170496000
    DDR_CLK 85248000
    TxByteClkHS 21312000
    LP_CLK 9472000

    Let me know how it goes.

    Regards

    Rafael

  • Hi Rafael

     

    I think the settings  the same as like that we expect.

    But I got a error here.

    [    8.412994] omapdss DSI error: DSI error, irqstatus 400a0

    I think is caused by DSI_IRQ_SYNC_LOST.

    How could we fix this error??

    thank you.

    ========Kernel message =========

    [    5.258270] omapdss DISPC: channel 0 xres 320 yres 480
    [    5.258270] omapdss DISPC: pck 10656
    [    5.258270] omapdss DISPC: hsw 4 hfp 10 hbp 3 vsw 2 vfp 43 vbp 2
    [    5.258270] omapdss DISPC: hsync 31620Hz, vsync 60Hz
    [    5.258300] omapdss DSI: PLL init
    [    5.618957] android_work: did not send uevent (1 1   (null))
    [    5.625244] omapdss DSI: PLL init done
    [    5.628417] mmc1: queuing unknown CIS tuple 0x91 (3 bytes)
    [    5.633850] mmc1: new SDIO card at address 0001
    [    5.639801] omapdss DSI: dsi_pll_set_clock_div()
    [    5.644714] omapdss DSI: DSI Fint 1536000
    [    5.644714] android_work: sent uevent USB_STATE=DISCONNECTED
    [    5.654907] omapdss DSI: clkin (dss_sys_clk) rate 38400000, highfreq 0
    [    5.661865] omapdss DSI: CLKIN4DDR = 2 * 111 / 25 * 38400000 / 1 = 340992000
    [    5.669342] omapdss DSI: Data rate on 1 DSI lane 170 Mbps
    [    5.675048] omapdss DSI: Clock lane freq 85248000 Hz
    [    5.680328] omapdss DSI: regm_dispc = 2, DSI_PLL_HSDIV_DISPC (PLL1_CLK1) = 170496000
    [    5.688507] omapdss DSI: regm_dsi = 2, DSI_PLL_HSDIV_DSI (PLL1_CLK2) = 170496000
    [    5.696319] omapdss DSI: PLL config done
    [    5.698944] omapdss DSI: PLL OK
    [    5.703918] omapdss DISPC: lck = 170496000 (1)
    [    5.706756] omapdss DISPC: pck = 10656000 (16)

     

     

    ===========================cat d/omapdss/dsi1_regs============================
    DSI_REVISION                        00000030
    DSI_SYSCONFIG                       00000011
    DSI_SYSSTATUS                       00000001
    DSI_IRQSTATUS                       00000000
    DSI_IRQENABLE                       0015c000
    DSI_CTRL                            00eaea18
    DSI_COMPLEXIO_CFG1                  6a000021
    DSI_COMPLEXIO_IRQ_STATUS            00000000
    DSI_COMPLEXIO_IRQ_ENABLE            3ff07fff
    DSI_CLK_CTRL                        a0346009
    DSI_TIMING1                         7fff7fff
    DSI_TIMING2                         7fff7fff
    DSI_VM_TIMING1                      ff011009
    DSI_VM_TIMING2                      04022b02
    DSI_VM_TIMING3                      02a101e0
    DSI_CLK_TIMING                      00000e0f
    DSI_TX_FIFO_VC_SIZE                 13121110
    DSI_RX_FIFO_VC_SIZE                 13121110
    DSI_COMPLEXIO_CFG2                  00000000
    DSI_RX_FIFO_VC_FULLNESS             00000000
    DSI_VM_TIMING4                      00487296
    DSI_TX_FIFO_VC_EMPTINESS            00000000
    DSI_VM_TIMING5                      0082df3b
    DSI_VM_TIMING6                      7a6731d1
    DSI_VM_TIMING7                      0012000f
    DSI_STOPCLK_TIMING                  00000080
    DSI_VC_CTRL(0)                      20800f90
    DSI_VC_TE(0)                        00000000
    DSI_VC_LONG_PACKET_HEADER(0)        00000000
    DSI_VC_LONG_PACKET_PAYLOAD(0)       00000000
    DSI_VC_SHORT_PACKET_HEADER(0)       00000000
    DSI_VC_IRQSTATUS(0)                 00000004
    DSI_VC_IRQENABLE(0)                 000000db
    DSI_VC_CTRL(1)                      20800f80
    DSI_VC_TE(1)                        00000000
    DSI_VC_LONG_PACKET_HEADER(1)        00000000
    DSI_VC_LONG_PACKET_PAYLOAD(1)       00000000
    DSI_VC_SHORT_PACKET_HEADER(1)       00000000
    DSI_VC_IRQSTATUS(1)                 00000000
    DSI_VC_IRQENABLE(1)                 000000db
    DSI_VC_CTRL(2)                      20800d80
    DSI_VC_TE(2)                        00000000
    DSI_VC_LONG_PACKET_HEADER(2)        00000000
    DSI_VC_LONG_PACKET_PAYLOAD(2)       00000000
    DSI_VC_SHORT_PACKET_HEADER(2)       00000000
    DSI_VC_IRQSTATUS(2)                 00000000
    DSI_VC_IRQENABLE(2)                 000000db
    DSI_VC_CTRL(3)                      20800d80
    DSI_VC_TE(3)                        00000000
    DSI_VC_LONG_PACKET_HEADER(3)        00000000
    DSI_VC_LONG_PACKET_PAYLOAD(3)       00000000
    DSI_VC_SHORT_PACKET_HEADER(3)       00000000
    DSI_VC_IRQSTATUS(3)                 00000000
    DSI_VC_IRQENABLE(3)                 000000db
    DSI_DSIPHY_CFG0                     08110b0d
    DSI_DSIPHY_CFG1                     42030817
    DSI_DSIPHY_CFG2                     b8000006
    DSI_DSIPHY_CFG5                     e3000000
    DSI_PLL_CONTROL                     00000000
    DSI_PLL_STATUS                      00000383
    DSI_PLL_GO                          00000000
    DSI_PLL_CONFIGURATION1              0420de31
    DSI_PLL_CONFIGURATION2              00656008
    ==================cat d/omapdss/dispc    ========================
    DISPC_REVISION                                     00000040
    DISPC_SYSCONFIG                                    00002015
    DISPC_SYSSTATUS                                    00000001
    DISPC_IRQSTATUS                                    00000020
    DISPC_IRQENABLE                                    0012d640
    DISPC_CONTROL                                      00018109
    DISPC_CONFIG                                       00020004
    DISPC_CAPABLE                                      00000000
    DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD)          00000000
    DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT)        00000000
    DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD)            00000000
    DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT)          00000000
    DISPC_LINE_STATUS                                  000000f9
    DISPC_LINE_NUMBER                                  00000000
    DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD)               00200903
    DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD)               00202b01
    DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD)               00000000
    DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD)               00010010
    DISPC_GLOBAL_ALPHA                                 ffffffff
    DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT)             00000000
    DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD)               01df013f
    DISPC_CONTROL2                                     00000000
    DISPC_CONFIG2                                      00000000
    DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2)         00000000
    DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2)           00000000
    DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD2)              00000000
    DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD2)              00000000
    DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD2)              00000000
    DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD2)              00040001
    DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD2)              00000000
    DISPC_OVL_BA0(OMAP_DSS_GFX)                        bd04b000
    DISPC_OVL_BA1(OMAP_DSS_GFX)                        bd04b000
    DISPC_OVL_POSITION(OMAP_DSS_GFX)                   00000000
    DISPC_OVL_SIZE(OMAP_DSS_GFX)                       01df013f
    DISPC_OVL_ATTRIBUTES(OMAP_DSS_GFX)                 0200008d
    DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_GFX)             04ff0098
    DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_GFX)           00000500
    DISPC_OVL_ROW_INC(OMAP_DSS_GFX)                    00000001
    DISPC_OVL_PIXEL_INC(OMAP_DSS_GFX)                  00000001
    DISPC_OVL_WINDOW_SKIP(OMAP_DSS_GFX)                00000000
    DISPC_OVL_TABLE_BA(OMAP_DSS_GFX)                   00000000
    DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD)            00000000
    DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD)            00000000
    DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD)            00000000
    DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD)             00000000
    DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD)             00000000
    DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD)             00000000
    DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2)           00000000
    DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2)           00000000
    DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2)           00000000
    DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2)            00000000
    DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2)            00000000
    DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2)            00000000
    DISPC_OVL_PRELOAD(OMAP_DSS_GFX)                    000004ff
    DISPC_OVL_BA0(o)                                   00000000
    DISPC_OVL_BA1(o)                                   00000000
    DISPC_OVL_POSITION(o)                              00000000
    DISPC_OVL_SIZE(o)                                  00000000
    DISPC_OVL_ATTRIBUTES(o)                            00008400
    DISPC_OVL_FIFO_THRESHOLD(o)                        07ff07f8
    DISPC_OVL_FIFO_SIZE_STATUS(o)                      00000800
    DISPC_OVL_ROW_INC(o)                               00000001
    DISPC_OVL_PIXEL_INC(o)                             00000001
    DISPC_OVL_FIR(o)                                   04000400
    DISPC_OVL_PICTURE_SIZE(o)                          00000000
    DISPC_OVL_ACCU0(o)                                 00000000
    DISPC_OVL_ACCU1(o)                                 00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_BA0_UV(o)                                00000000
    DISPC_OVL_BA1_UV(o)                                00000000
    DISPC_OVL_FIR2(o)                                  04000400
    DISPC_OVL_ACCU2_0(o)                               00000000
    DISPC_OVL_ACCU2_1(o)                               00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_ATTRIBUTES2(o)                           00000000
    DISPC_OVL_PRELOAD(o)                               00000100
    DISPC_OVL_BA0(o)                                   00000000
    DISPC_OVL_BA1(o)                                   00000000
    DISPC_OVL_POSITION(o)                              00000000
    DISPC_OVL_SIZE(o)                                  00000000
    DISPC_OVL_ATTRIBUTES(o)                            00008400
    DISPC_OVL_FIFO_THRESHOLD(o)                        07ff07f8
    DISPC_OVL_FIFO_SIZE_STATUS(o)                      00000800
    DISPC_OVL_ROW_INC(o)                               00000001
    DISPC_OVL_PIXEL_INC(o)                             00000001
    DISPC_OVL_FIR(o)                                   04000400
    DISPC_OVL_PICTURE_SIZE(o)                          00000000
    DISPC_OVL_ACCU0(o)                                 00000000
    DISPC_OVL_ACCU1(o)                                 00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_BA0_UV(o)                                00000000
    DISPC_OVL_BA1_UV(o)                                00000000
    DISPC_OVL_FIR2(o)                                  04000400
    DISPC_OVL_ACCU2_0(o)                               00000000
    DISPC_OVL_ACCU2_1(o)                               00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_ATTRIBUTES2(o)                           00000000
    DISPC_OVL_PRELOAD(o)                               00000100
    DISPC_OVL_BA0(o)                                   00000000
    DISPC_OVL_BA1(o)                                   00000000
    DISPC_OVL_POSITION(o)                              00000000
    DISPC_OVL_SIZE(o)                                  00000000
    DISPC_OVL_ATTRIBUTES(o)                            00008400
    DISPC_OVL_FIFO_THRESHOLD(o)                        07ff07f8
    DISPC_OVL_FIFO_SIZE_STATUS(o)                      00000800
    DISPC_OVL_ROW_INC(o)                               00000001
    DISPC_OVL_PIXEL_INC(o)                             00000001
    DISPC_OVL_FIR(o)                                   04000400
    DISPC_OVL_PICTURE_SIZE(o)                          00000000
    DISPC_OVL_ACCU0(o)                                 00000000
    DISPC_OVL_ACCU1(o)                                 00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_BA0_UV(o)                                00000000
    DISPC_OVL_BA1_UV(o)                                00000000
    DISPC_OVL_FIR2(o)                                  04000400
    DISPC_OVL_ACCU2_0(o)                               00000000
    DISPC_OVL_ACCU2_1(o)                               00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_ATTRIBUTES2(o)                           00000000
    DISPC_OVL_PRELOAD(o)                               00000100
    ======================d/omapdss/clk===================                                            
    - DSS -
    dpll4_ck 1536000000
    DSS_FCK (DSS_FCLK) = 1536000000 / 9  = 170666666
    - DISPC -
    dispc fclk source = DSI_PLL_HSDIV_DISPC (PLL1_CLK1)
    fck  170496000      
    - DISPC-CORE-CLK -
    lck  170496000       lck div 1
    - LCD1 -
    lcd1_clk source = DSI_PLL_HSDIV_DISPC (PLL1_CLK1)
    lck  170496000       lck div 1
    pck  10656000        pck div 16
    - LCD2 -
    lcd2_clk source = DSS_FCK (DSS_FCLK)
    lck  42666666        lck div 4
    pck  42666666        pck div 1
    - DSI1 PLL -
    dsi pll source = dss_sys_clk
    Fint  1536000         regn 25
    CLKIN4DDR 340992000       regm 111
    DSI_PLL_HSDIV_DISPC (PLL1_CLK1) 170496000       regm_dispc 2 (on)
    DSI_PLL_HSDIV_DSI (PLL1_CLK2) 170496000       regm_dsi 2 (on)
    - DSI1 -
    dsi fclk source = DSI_PLL_HSDIV_DSI (PLL1_CLK2)
    DSI_FCLK 170496000
    DDR_CLK  85248000
    TxByteClkHS 21312000
    LP_CLK  9472000

     

  • Hi Wu

    The following registers draw my attention. You have:

    DSI_VM_TIMING1                      ff011009
    DSI_VM_TIMING3                      02a101e0
    DSI_TX_FIFO_VC_EMPTINESS   00000000

    You should have
    DSI_VM_TIMING1                      0001200a               00000000              000000010010    000000001010
                                                                                    DSI_HSA=0            DSI_HFP=18      DSI_HBP=10
    DSI_VM_TIMING3                      02a201e0             0000001010100010         0000000111100000
                                                                                      TL= 674                          VACT=480
     
    DSI_TX_FIFO_VC_EMPTINESS            1f1f001

    Fix them and let me know how it goes.
    For Blaze, these registers are calculated and written in drivers/video/omap2/dss/dsi.c
    Regards
    Rafael
  • Any news Wu? Were you able to change those registers?

  • Dear Rafael

    It's very strange here.

    dsi.c subtract 1 from those parameters

     I think we have the same value here.

    hsa=0  hbp=10  hfp=18  tl =674

    Sould we modify those formula ?

    static int dsi_video_proto_config(struct omap_dss_device *dssdev)

    {

     

    //  dsi_video_proto_config : hsa=0  hbp=10  hfp=18  tl =674

    r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
     r = FLD_MOD(r, hbp - 1, 11, 0);   /* HBP */
     r = FLD_MOD(r, hfp - 1, 23, 12);  /* HFP */
     r = FLD_MOD(r, hsa - 1, 31, 24);  /* HSA */
     dsi_write_reg(dsidev, DSI_VM_TIMING1, r); r = dsi_read_reg(dsidev, DSI_VM_TIMING1);

     

     r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
     r = FLD_MOD(r, timings->y_res, 14, 0);
     r = FLD_MOD(r, tl - 1, 31, 16);
     dsi_write_reg(dsidev, DSI_VM_TIMING3, r);

    }

     

  • Yes. For now change it. That calculation has changed in newer kernel versions.
    The critical part is tl. 
    There is another change I would like you to test, after that
    On  panda4460_lcd_device
    .hfp = 12,
    .hsw = 4,
    .hbp = 1,

    And on dsi_video_proto_config

    DSI_VM_TIMING1
    HSA = 0
    HFP = 18
    HBP = 6
    DSI_VM_TIMING3
    TL = 674
    VACT = 480


  • Dear Rafael

     

    We haven't seem any display on panel when using setting 1, but haven't any error message.

    .clocks = {
                 .dispc = {
                         .channel = {
                               .lck_div        = 1,
                               .pck_div        = 16,
                               .lcd_clk_src    = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
                        },
                        .dispc_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
                 },

     

                 .dsi = {
                        .regn           = 25,
                        .regm           = 111,
                        .regm_dispc     = 2,
                        .regm_dsi       = 2,
                        .lp_clk_div     = 9,
                        .offset_ddr_clk = 0,
                        .dsi_fclk_src   = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,
                 },
           },

     

           .panel = {
                 .timings = {
                        .x_res       = 320,
                        .y_res       = 480,
                        .pixel_clock = 10656,
                        .hfp         = 10,
                               .hsw         = 4,
                        .hbp         = 3,
                        .vfp         = 43,
                        .vsw         = 2,
                        .vbp         = 2,
                 },
           },

     

           .ctrl = {
                 .pixel_size = 16,
           },

    Here is the setting 1 register value

     

    ================================ cat d/omapdss/dispc     ================================                                      
    DISPC_REVISION                                     00000040
    DISPC_SYSCONFIG                                    00002015
    DISPC_SYSSTATUS                                    00000001
    DISPC_IRQSTATUS                                    00000020
    DISPC_IRQENABLE                                    0012d640
    DISPC_CONTROL                                      00018109
    DISPC_CONFIG                                       00020004
    DISPC_CAPABLE                                      00000000
    DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD)          00000000
    DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT)        00000000
    DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD)            00000000
    DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT)          00000000
    DISPC_LINE_STATUS                                  000001bd
    DISPC_LINE_NUMBER                                  00000000
    DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD)               00200903
    DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD)               00202b01
    DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD)               00000000
    DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD)               00010010
    DISPC_GLOBAL_ALPHA                                 ffffffff
    DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT)             00000000
    DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD)               01df013f
    DISPC_CONTROL2                                     00000000
    DISPC_CONFIG2                                      00000000
    DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2)         00000000
    DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2)           00000000
    DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD2)              00000000
    DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD2)              00000000
    DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD2)              00000000
    DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD2)              00040001
    DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD2)              00000000
    DISPC_OVL_BA0(OMAP_DSS_GFX)                        bd04b000
    DISPC_OVL_BA1(OMAP_DSS_GFX)                        bd04b000
    DISPC_OVL_POSITION(OMAP_DSS_GFX)                   00000000
    DISPC_OVL_SIZE(OMAP_DSS_GFX)                       01df013f
    DISPC_OVL_ATTRIBUTES(OMAP_DSS_GFX)                 0200008d
    DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_GFX)             04ff0098
    DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_GFX)           00000500
    DISPC_OVL_ROW_INC(OMAP_DSS_GFX)                    00000001
    DISPC_OVL_PIXEL_INC(OMAP_DSS_GFX)                  00000001
    DISPC_OVL_WINDOW_SKIP(OMAP_DSS_GFX)                00000000
    DISPC_OVL_TABLE_BA(OMAP_DSS_GFX)                   00000000
    DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD)            00000000
    DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD)            00000000
    DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD)            00000000
    DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD)             00000000
    DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD)             00000000
    DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD)             00000000
    DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2)           00000000
    DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2)           00000000
    DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2)           00000000
    DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2)            00000000
    DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2)            00000000
    DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2)            00000000
    DISPC_OVL_PRELOAD(OMAP_DSS_GFX)                    000004ff
    DISPC_OVL_BA0(o)                                   00000000
    DISPC_OVL_BA1(o)                                   00000000
    DISPC_OVL_POSITION(o)                              00000000
    DISPC_OVL_SIZE(o)                                  00000000
    DISPC_OVL_ATTRIBUTES(o)                            00008400
    DISPC_OVL_FIFO_THRESHOLD(o)                        07ff07f8
    DISPC_OVL_FIFO_SIZE_STATUS(o)                      00000800
    DISPC_OVL_ROW_INC(o)                               00000001
    DISPC_OVL_PIXEL_INC(o)                             00000001
    DISPC_OVL_FIR(o)                                   04000400
    DISPC_OVL_PICTURE_SIZE(o)                          00000000
    DISPC_OVL_ACCU0(o)                                 00000000
    DISPC_OVL_ACCU1(o)                                 00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_BA0_UV(o)                                00000000
    DISPC_OVL_BA1_UV(o)                                00000000
    DISPC_OVL_FIR2(o)                                  04000400
    DISPC_OVL_ACCU2_0(o)                               00000000
    DISPC_OVL_ACCU2_1(o)                               00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_ATTRIBUTES2(o)                           00000000
    DISPC_OVL_PRELOAD(o)                               00000100
    DISPC_OVL_BA0(o)                                   00000000
    DISPC_OVL_BA1(o)                                   00000000
    DISPC_OVL_POSITION(o)                              00000000
    DISPC_OVL_SIZE(o)                                  00000000
    DISPC_OVL_ATTRIBUTES(o)                            00008400
    DISPC_OVL_FIFO_THRESHOLD(o)                        07ff07f8
    DISPC_OVL_FIFO_SIZE_STATUS(o)                      00000800
    DISPC_OVL_ROW_INC(o)                               00000001
    DISPC_OVL_PIXEL_INC(o)                             00000001
    DISPC_OVL_FIR(o)                                   04000400
    DISPC_OVL_PICTURE_SIZE(o)                          00000000
    DISPC_OVL_ACCU0(o)                                 00000000
    DISPC_OVL_ACCU1(o)                                 00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_BA0_UV(o)                                00000000
    DISPC_OVL_BA1_UV(o)                                00000000
    DISPC_OVL_FIR2(o)                                  04000400
    DISPC_OVL_ACCU2_0(o)                               00000000
    DISPC_OVL_ACCU2_1(o)                               00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_ATTRIBUTES2(o)                           00000000
    DISPC_OVL_PRELOAD(o)                               00000100
    DISPC_OVL_BA0(o)                                   00000000
    DISPC_OVL_BA1(o)                                   00000000
    DISPC_OVL_POSITION(o)                              00000000
    DISPC_OVL_SIZE(o)                                  00000000
    DISPC_OVL_ATTRIBUTES(o)                            00008400
    DISPC_OVL_FIFO_THRESHOLD(o)                        07ff07f8
    DISPC_OVL_FIFO_SIZE_STATUS(o)                      00000800
    DISPC_OVL_ROW_INC(o)                               00000001
    DISPC_OVL_PIXEL_INC(o)                             00000001
    DISPC_OVL_FIR(o)                                   04000400
    DISPC_OVL_PICTURE_SIZE(o)                          00000000
    DISPC_OVL_ACCU0(o)                                 00000000
    DISPC_OVL_ACCU1(o)                                 00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_BA0_UV(o)                                00000000
    DISPC_OVL_BA1_UV(o)                                00000000
    DISPC_OVL_FIR2(o)                                  04000400
    DISPC_OVL_ACCU2_0(o)                               00000000
    DISPC_OVL_ACCU2_1(o)                               00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_ATTRIBUTES2(o)                           00000000
    DISPC_OVL_PRELOAD(o)                               00000100
    ==========================# cat d/omapdss/dsi1_regs ==================                                      
    DSI_REVISION                        00000030
    DSI_SYSCONFIG                       00000011
    DSI_SYSSTATUS                       00000001
    DSI_IRQSTATUS                       00000080
    DSI_IRQENABLE                       0015c000
    DSI_CTRL                            00eaea19
    DSI_COMPLEXIO_CFG1                  6a000021
    DSI_COMPLEXIO_IRQ_STATUS            00000000
    DSI_COMPLEXIO_IRQ_ENABLE            3ff07fff
    DSI_CLK_CTRL                        a0346009
    DSI_TIMING1                         7fff7fff
    DSI_TIMING2                         ffff7fff
    DSI_VM_TIMING1                      0001200a <== Correct
    DSI_VM_TIMING2                      04022b02
    DSI_VM_TIMING3                      02a201e0 <== Correct
    DSI_CLK_TIMING                      00000e0f
    DSI_TX_FIFO_VC_SIZE                 13121110
    DSI_RX_FIFO_VC_SIZE                 13121110
    DSI_COMPLEXIO_CFG2                  00030000
    DSI_RX_FIFO_VC_FULLNESS             00000000
    DSI_VM_TIMING4                      00487296
    DSI_TX_FIFO_VC_EMPTINESS            1f1f1f1f <== Correct
    DSI_VM_TIMING5                      0082df3b
    DSI_VM_TIMING6                      7a6731d1
    DSI_VM_TIMING7                      0012000f
    DSI_STOPCLK_TIMING                  00000080
    DSI_VC_CTRL(0)                      20808f91
    DSI_VC_TE(0)                        00000000
    DSI_VC_LONG_PACKET_HEADER(0)        00000000
    DSI_VC_LONG_PACKET_PAYLOAD(0)       00000000
    DSI_VC_SHORT_PACKET_HEADER(0)       00000000
    DSI_VC_IRQSTATUS(0)                 00000004
    DSI_VC_IRQENABLE(0)                 000000db
    DSI_VC_CTRL(1)                      20808f81
    DSI_VC_TE(1)                        00000000
    DSI_VC_LONG_PACKET_HEADER(1)        00000000
    DSI_VC_LONG_PACKET_PAYLOAD(1)       00000000
    DSI_VC_SHORT_PACKET_HEADER(1)       00000000
    DSI_VC_IRQSTATUS(1)                 00000000
    DSI_VC_IRQENABLE(1)                 000000db
    DSI_VC_CTRL(2)                      20808d81
    DSI_VC_TE(2)                        00000000
    DSI_VC_LONG_PACKET_HEADER(2)        00000000
    DSI_VC_LONG_PACKET_PAYLOAD(2)       00000000
    DSI_VC_SHORT_PACKET_HEADER(2)       00000000
    DSI_VC_IRQSTATUS(2)                 00000000
    DSI_VC_IRQENABLE(2)                 000000db
    DSI_VC_CTRL(3)                      20808d81
    DSI_VC_TE(3)                        00000000
    DSI_VC_LONG_PACKET_HEADER(3)        00000000
    DSI_VC_LONG_PACKET_PAYLOAD(3)       00000000
    DSI_VC_SHORT_PACKET_HEADER(3)       00000000
    DSI_VC_IRQSTATUS(3)                 00000000
    DSI_VC_IRQENABLE(3)                 000000db
    DSI_DSIPHY_CFG0                     08110b0d
    DSI_DSIPHY_CFG1                     42030817
    DSI_DSIPHY_CFG2                     b8000006
    DSI_DSIPHY_CFG5                     e3000000
    DSI_PLL_CONTROL                     00000000
    DSI_PLL_STATUS                      00000383
    DSI_PLL_GO                          00000000
    DSI_PLL_CONFIGURATION1              0420de31
    DSI_PLL_CONFIGURATION2              00656008
    ============================   cat d/omapdss/clk      =====================================                                      
    - DSS -
    dpll4_ck 1536000000
    DSS_FCK (DSS_FCLK) = 1536000000 / 9  = 170666666
    - DISPC -
    dispc fclk source = DSI_PLL_HSDIV_DISPC (PLL1_CLK1)
    fck  170496000      
    - DISPC-CORE-CLK -
    lck  170496000       lck div 1
    - LCD1 -
    lcd1_clk source = DSI_PLL_HSDIV_DISPC (PLL1_CLK1)
    lck  170496000       lck div 1
    pck  10656000        pck div 16
    - LCD2 -
    lcd2_clk source = DSS_FCK (DSS_FCLK)
    lck  42666666        lck div 4
    pck  42666666        pck div 1
    - DSI1 PLL -
    dsi pll source = dss_sys_clk
    Fint  1536000         regn 25
    CLKIN4DDR 340992000       regm 111
    DSI_PLL_HSDIV_DISPC (PLL1_CLK1) 170496000       regm_dispc 2 (on)
    DSI_PLL_HSDIV_DSI (PLL1_CLK2) 170496000       regm_dsi 2 (on)
    - DSI1 -
    dsi fclk source = DSI_PLL_HSDIV_DSI (PLL1_CLK2)
    DSI_FCLK 170496000
    DDR_CLK  85248000
    TxByteClkHS 21312000
    LP_CLK  9472000

     

     

    Settings 2 haven't display on panel , and haven't any error here.

    But value haven't match here

    expect value

    DSI_VM_TIMING1
    HSA = 0
    HFP = 18
    HBP = 6
    DSI_VM_TIMING3
    TL = 674
    VACT = 48
     
    Result vaue
    DSI_VM_TIMING1
    hsa=0
    hfp=22 
    hbp=6   
    DSI_VM_TIMING3 
    tl=674
    vact=480  
     
    HFP formula is ( val = timings->hfp - 1 here is 12 -1 = 11, bytes_per_pixel = 2 , lane = 1)
    static int dispc_to_dsi_clock(int val, int bytes_per_pixel, int lanes)
    {
     return (val * bytes_per_pixel + lanes / 2) / lanes; // ( 11 * 2 + 1 / 2 ) / 1 = 22.5 , return int type is 22
    }

    ====================  cat d/omapdss/dsi1_regs         =============================                             
    DSI_REVISION                        00000030
    DSI_SYSCONFIG                       00000011
    DSI_SYSSTATUS                       00000001
    DSI_IRQSTATUS                       00000080
    DSI_IRQENABLE                       0015c000
    DSI_CTRL                            00eaea19
    DSI_COMPLEXIO_CFG1                  6a000021
    DSI_COMPLEXIO_IRQ_STATUS            00000000
    DSI_COMPLEXIO_IRQ_ENABLE            3ff07fff
    DSI_CLK_CTRL                        a0346009
    DSI_TIMING1                         7fff7fff
    DSI_TIMING2                         ffff7fff
    DSI_VM_TIMING1                      00016006
    DSI_VM_TIMING2                      04022b02
    DSI_VM_TIMING3                      02a201e0
    DSI_CLK_TIMING                      00000e0f
    DSI_TX_FIFO_VC_SIZE                 13121110
    DSI_RX_FIFO_VC_SIZE                 13121110
    DSI_COMPLEXIO_CFG2                  00030000
    DSI_RX_FIFO_VC_FULLNESS             00000000
    DSI_VM_TIMING4                      00487296
    DSI_TX_FIFO_VC_EMPTINESS            1f1f1f1f
    DSI_VM_TIMING5                      0082df3b
    DSI_VM_TIMING6                      7a6731d1
    DSI_VM_TIMING7                      0012000f
    DSI_STOPCLK_TIMING                  00000080
    DSI_VC_CTRL(0)                      20808f91
    DSI_VC_TE(0)                        00000000
    DSI_VC_LONG_PACKET_HEADER(0)        00000000
    DSI_VC_LONG_PACKET_PAYLOAD(0)       00000000
    DSI_VC_SHORT_PACKET_HEADER(0)       00000000
    DSI_VC_IRQSTATUS(0)                 00000004
    DSI_VC_IRQENABLE(0)                 000000db
    DSI_VC_CTRL(1)                      20808f81
    DSI_VC_TE(1)                        00000000
    DSI_VC_LONG_PACKET_HEADER(1)        00000000
    DSI_VC_LONG_PACKET_PAYLOAD(1)       00000000
    DSI_VC_SHORT_PACKET_HEADER(1)       00000000
    DSI_VC_IRQSTATUS(1)                 00000000
    DSI_VC_IRQENABLE(1)                 000000db
    DSI_VC_CTRL(2)                      20808d81
    DSI_VC_TE(2)                        00000000
    DSI_VC_LONG_PACKET_HEADER(2)        00000000
    DSI_VC_LONG_PACKET_PAYLOAD(2)       00000000
    DSI_VC_SHORT_PACKET_HEADER(2)       00000000
    DSI_VC_IRQSTATUS(2)                 00000000
    DSI_VC_IRQENABLE(2)                 000000db
    DSI_VC_CTRL(3)                      20808d81
    DSI_VC_TE(3)                        00000000
    DSI_VC_LONG_PACKET_HEADER(3)        00000000
    DSI_VC_LONG_PACKET_PAYLOAD(3)       00000000
    DSI_VC_SHORT_PACKET_HEADER(3)       00000000
    DSI_VC_IRQSTATUS(3)                 00000000
    DSI_VC_IRQENABLE(3)                 000000db
    DSI_DSIPHY_CFG0                     08110b0d
    DSI_DSIPHY_CFG1                     42030817
    DSI_DSIPHY_CFG2                     b8000006
    DSI_DSIPHY_CFG5                     e3000000
    DSI_PLL_CONTROL                     00000000
    DSI_PLL_STATUS                      00000383
    DSI_PLL_GO                          00000000
    DSI_PLL_CONFIGURATION1              0420de31
    DSI_PLL_CONFIGURATION2              00656008
    ======================== cat d/omapdss/dispc           ==========================                               
    DISPC_REVISION                                     00000040
    DISPC_SYSCONFIG                                    00002015
    DISPC_SYSSTATUS                                    00000001
    DISPC_IRQSTATUS                                    000000a0
    DISPC_IRQENABLE                                    0016d64e
    DISPC_CONTROL                                      00018129
    DISPC_CONFIG                                       00020004
    DISPC_CAPABLE                                      00000000
    DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD)          00000000
    DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT)        00000000
    DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD)            00000000
    DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT)          00000000
    DISPC_LINE_STATUS                                  000001b5
    DISPC_LINE_NUMBER                                  00000000
    DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD)               00000b03
    DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD)               00202b01
    DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD)               00000000
    DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD)               00010010
    DISPC_GLOBAL_ALPHA                                 ffffffff
    DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT)             00000000
    DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD)               01df013f
    DISPC_CONTROL2                                     00000000
    DISPC_CONFIG2                                      00000000
    DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2)         00000000
    DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2)           00000000
    DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD2)              00000000
    DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD2)              00000000
    DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD2)              00000000
    DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD2)              00040001
    DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD2)              00000000
    DISPC_OVL_BA0(OMAP_DSS_GFX)                        bd000000
    DISPC_OVL_BA1(OMAP_DSS_GFX)                        bd000000
    DISPC_OVL_POSITION(OMAP_DSS_GFX)                   00000000
    DISPC_OVL_SIZE(OMAP_DSS_GFX)                       01df013f
    DISPC_OVL_ATTRIBUTES(OMAP_DSS_GFX)                 0200008d
    DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_GFX)             04ff0098
    DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_GFX)           00000500
    DISPC_OVL_ROW_INC(OMAP_DSS_GFX)                    00000001
    DISPC_OVL_PIXEL_INC(OMAP_DSS_GFX)                  00000001
    DISPC_OVL_WINDOW_SKIP(OMAP_DSS_GFX)                00000000
    DISPC_OVL_TABLE_BA(OMAP_DSS_GFX)                   00000000
    DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD)            00000000
    DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD)            00000000
    DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD)            00000000
    DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD)             00000000
    DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD)             00000000
    DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD)             00000000
    DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2)           00000000
    DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2)           00000000
    DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2)           00000000
    DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2)            00000000
    DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2)            00000000
    DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2)            00000000
    DISPC_OVL_PRELOAD(OMAP_DSS_GFX)                    000004ff
    DISPC_OVL_BA0(o)                                   00000000
    DISPC_OVL_BA1(o)                                   00000000
    DISPC_OVL_POSITION(o)                              00000000
    DISPC_OVL_SIZE(o)                                  00000000
    DISPC_OVL_ATTRIBUTES(o)                            00008400
    DISPC_OVL_FIFO_THRESHOLD(o)                        07ff07f8
    DISPC_OVL_FIFO_SIZE_STATUS(o)                      00000800
    DISPC_OVL_ROW_INC(o)                               00000001
    DISPC_OVL_PIXEL_INC(o)                             00000001
    DISPC_OVL_FIR(o)                                   04000400
    DISPC_OVL_PICTURE_SIZE(o)                          00000000
    DISPC_OVL_ACCU0(o)                                 00000000
    DISPC_OVL_ACCU1(o)                                 00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_BA0_UV(o)                                00000000
    DISPC_OVL_BA1_UV(o)                                00000000
    DISPC_OVL_FIR2(o)                                  04000400
    DISPC_OVL_ACCU2_0(o)                               00000000
    DISPC_OVL_ACCU2_1(o)                               00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_ATTRIBUTES2(o)                           00000000
    DISPC_OVL_PRELOAD(o)                               00000100
    DISPC_OVL_BA0(o)                                   00000000
    DISPC_OVL_BA1(o)                                   00000000
    DISPC_OVL_POSITION(o)                              00000000
    DISPC_OVL_SIZE(o)                                  00000000
    DISPC_OVL_ATTRIBUTES(o)                            00008400
    DISPC_OVL_FIFO_THRESHOLD(o)                        07ff07f8
    DISPC_OVL_FIFO_SIZE_STATUS(o)                      00000800
    DISPC_OVL_ROW_INC(o)                               00000001
    DISPC_OVL_PIXEL_INC(o)                             00000001
    DISPC_OVL_FIR(o)                                   04000400
    DISPC_OVL_PICTURE_SIZE(o)                          00000000
    DISPC_OVL_ACCU0(o)                                 00000000
    DISPC_OVL_ACCU1(o)                                 00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_BA0_UV(o)                                00000000
    DISPC_OVL_BA1_UV(o)                                00000000
    DISPC_OVL_FIR2(o)                                  04000400
    DISPC_OVL_ACCU2_0(o)                               00000000
    DISPC_OVL_ACCU2_1(o)                               00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_ATTRIBUTES2(o)                           00000000
    DISPC_OVL_PRELOAD(o)                               00000100
    DISPC_OVL_BA0(o)                                   00000000
    DISPC_OVL_BA1(o)                                   00000000
    DISPC_OVL_POSITION(o)                              00000000
    DISPC_OVL_SIZE(o)                                  00000000
    DISPC_OVL_ATTRIBUTES(o)                            00008400
    DISPC_OVL_FIFO_THRESHOLD(o)                        07ff07f8
    DISPC_OVL_FIFO_SIZE_STATUS(o)                      00000800
    DISPC_OVL_ROW_INC(o)                               00000001
    DISPC_OVL_PIXEL_INC(o)                             00000001
    DISPC_OVL_FIR(o)                                   04000400
    DISPC_OVL_PICTURE_SIZE(o)                          00000000
    DISPC_OVL_ACCU0(o)                                 00000000
    DISPC_OVL_ACCU1(o)                                 00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_BA0_UV(o)                                00000000
    DISPC_OVL_BA1_UV(o)                                00000000
    DISPC_OVL_FIR2(o)                                  04000400
    DISPC_OVL_ACCU2_0(o)                               00000000
    DISPC_OVL_ACCU2_1(o)                               00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_ATTRIBUTES2(o)                           00000000
    DISPC_OVL_PRELOAD(o)                               00000100
    ============= cat d/omapdss/clk          =======================                                   
    - DSS -
    dpll4_ck 1536000000
    DSS_FCK (DSS_FCLK) = 1536000000 / 9  = 170666666
    - DISPC -
    dispc fclk source = DSI_PLL_HSDIV_DISPC (PLL1_CLK1)
    fck  170496000      
    - DISPC-CORE-CLK -
    lck  170496000       lck div 1
    - LCD1 -
    lcd1_clk source = DSI_PLL_HSDIV_DISPC (PLL1_CLK1)
    lck  170496000       lck div 1
    pck  10656000        pck div 16
    - LCD2 -
    lcd2_clk source = DSS_FCK (DSS_FCLK)
    lck  42666666        lck div 4
    pck  42666666        pck div 1
    - DSI1 PLL -
    dsi pll source = dss_sys_clk
    Fint  1536000         regn 25
    CLKIN4DDR 340992000       regm 111
    DSI_PLL_HSDIV_DISPC (PLL1_CLK1) 170496000       regm_dispc 2 (on)
    DSI_PLL_HSDIV_DSI (PLL1_CLK2) 170496000       regm_dsi 2 (on)
    - DSI1 -
    dsi fclk source = DSI_PLL_HSDIV_DSI (PLL1_CLK2)
    DSI_FCLK 170496000
    DDR_CLK  85248000
    TxByteClkHS 21312000

     

     

     

  • Hi Wu

    I feel that the timings are correct now, (setting 1 should be fine) please review your panel datasheet for any additional configuration that may be needed.

    In the mean time, I will do the same and see if there is any additional restriction that I may have missed.

    I will get back to you soon.

    Regards

    Rafael

  • Hi Wu

    Any news?

    If you have not been successful, could you please try this configuration?

          .clocks = {
                 .dispc = {
                         .channel = {
                               .lck_div        = 1,
                               .pck_div        = 16,
                               .lcd_clk_src    = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
                        },
                        .dispc_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
                 },

     

                 .dsi = {
                        .regn           = 18,
                        .regm           = 87,
                        .regm_dispc     = 2,
                        .regm_dsi       = 2,
                        .lp_clk_div     = 9,
                        .offset_ddr_clk = 0,
                        .dsi_fclk_src   = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,
                 },
           },

     

           .panel = {
                 .timings = {
                        .x_res       = 320,
                        .y_res       = 480,
                        .pixel_clock = 11600,
                        .hfp         = 11,
                               .hsw         = 4,
                        .hbp         = 54,
                        .vfp         = 12,
                        .vsw         = 3,
                        .vbp         = 2,
                 },
           },

     

           .ctrl = {
                 .pixel_size = 16,
           },

    Then on dsi.c make sure you get his values:

    //  dsi_video_proto_config : hsa=0  hbp=112  hfp=20  tl =778
    r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
     r = FLD_MOD(r, 112, 11, 0);   /* HBP */
     r = FLD_MOD(r, 20, 23, 12);  /* HFP */
     r = FLD_MOD(r, 0, 31, 24);  /* HSA */
     dsi_write_reg(dsidev, DSI_VM_TIMING1, r);

     

     r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
     r = FLD_MOD(r, timings->y_res, 14, 0);
     r = FLD_MOD(r, 778, 31, 16);
     dsi_write_reg(dsidev, DSI_VM_TIMING3, r);

    If that doesn't work, try changing DSI blankigs above to:

    //  dsi_video_proto_config : hsa=0  hbp=108  hfp=20  tl =778

    Otherwise we'll try something else

    Let me know how it goes.

    Regards

    Rafael

  • Hi Rodriguez

    I have tried this settings.

    But haven't any fram on panel.

     

          .clocks = {
                 .dispc = {
                         .channel = {
                               .lck_div        = 1,
                               .pck_div        = 16,
                               .lcd_clk_src    = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
                        },
                        .dispc_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
                 },

     

                 .dsi = {
                        .regn           = 18,
                        .regm           = 87,
                        .regm_dispc     = 2,
                        .regm_dsi       = 2,
                        .lp_clk_div     = 9,
                        .offset_ddr_clk = 0,
                        .dsi_fclk_src   = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,
                 },
           },

     

           .panel = {
                 .timings = {
                        .x_res       = 320,
                        .y_res       = 480,
                        .pixel_clock = 11600,
                        .hfp         = 11,
                               .hsw         = 4,
                        .hbp         = 54,
                        .vfp         = 12,
                        .vsw         = 3,
                        .vbp         = 2,
                 },
           },

     

           .ctrl = {
                 .pixel_size = 16,
           },
     
    These value is correct on my settings.
    //  dsi_video_proto_config : hsa=0  hbp=112  hfp=20  tl =778
    r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
     r = FLD_MOD(r, 112, 11, 0);   /* HBP */
     r = FLD_MOD(r, 20, 23, 12);  /* HFP */
     r = FLD_MOD(r, 0, 31, 24);  /* HSA */
     dsi_write_reg(dsidev, DSI_VM_TIMING1, r);

     

     r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
     r = FLD_MOD(r, timings->y_res, 14, 0);
     r = FLD_MOD(r, 778, 31, 16);
     dsi_write_reg(dsidev, DSI_VM_TIMING3, r);

    I have tried these setting 
    //  dsi_video_proto_config : hsa=0  hbp=108  hfp=20  tl =778

     

    It has frame on panel (But only have flick line) when we use these setting below

    I have no idea that how to set correct value .

    16 Bit Pixel One lane speed => 240MHZ

    If we haven't reach the speed will be ok?

     .clocks = {
      .dispc = {
       .channel = {

        .lck_div = 1, /* LCD */// Logic clk 120MHz
        .pck_div =10, /* PCD */ //12MHz
     
        .lcd_clk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
       },
       .dispc_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
      },

      .dsi = {
       .regn  = 16, /* Fint = 2.4 MHz */
       .regm  = 100, /* DDR Clock = 480 MHz   One Lane speed = 240MHZ*/
       .regm_dispc = 4, /* PLL1_CLK1 = 120 MHz */
       .regm_dsi = 4, /* PLL1_CLK2 = 120 MHz */

       .lp_clk_div = 10, /* LP Clock = 8.64 MHz */

       .offset_ddr_clk = 0,
     
       .dsi_fclk_src   = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,
      },
     },

     

    .x_res  = 320,
    .y_res  = 480,
    .pixel_clock  = 12000,
    .hsw  = 3,
    .hfp  = 3,
    .hbp  = 3,
    .vsw  = 4,
    .vfp  = 4,
    .vbp  = 4,

     

  • Hi Rodriguez, William,

    I did not read in full details the post so please correct me if I am wrong.

    The panel is RGB18 pixels 2 DL command mode panel (with frame buffer). Therefore the code for Blaze should applied nearly straight forward.

    DISPC

    • You need to set DISPC output to RGB18 (TFTDATALINES=0x2) and in stall mode (STALLMODE=1)
    • To control frame rate i suggest you use the Tearing effect. Panel will request a new frame to OMAP. OMAP can be set to start trasfer manually or on a TE event.
    • No need to minimize DISPC Pixel clock.
    • no need to set H and V timing (only used for video mode), keep the same as blaze.

    DSI

    • Use max freq available for DSI CLOCK (450MHz) 
    • You do not have to set register named _vm (only used for video mode),
    • no need to set the pixel format in the packet (only used for video mode).
    • no need to set H and V timing (only used for video mode) keep the same as blaze.

    I have attached a configuration for a DSI_CLK of 400MHz, 2Dl, RGB18 with a Sysclock 38.4. The below is value which should be read in the OMAP registers

    DSI type CommandMode

    DSI_PROTOCOL_ENGINE

    •   DSI_CTRLn
             VP_DATA_BUS_WIDTH = 1
    •   DSI_CLK_CTRL
         LP_RX_SYNCHRO_ENABLE = 1
         DDR_CLK_ALWAYS_ON = 0
         LP_CLK_ENABLE = 1
         LP_CLK_DIVISOR = 18
    •   DSI_CLK_TIMING
         DDR_CLK_PRE = 46
         DDR_CLK_POST = 19
    •   DSI_VM_TIMING7
         ENTER_HS_MODE_LATENCY = 27
         EXIT_HS_MODE_LATENCY = 23
    •   DSI_STOPCLK_TIMING (assumes worst case OPP50)
         DSI_STOPCLK_LATENCY = 6
    •   DSI_VM_TIMING8
         HFPX = 0
    •   DSI_VC_CTRL_0
         MODE = 0
         SOURCE = 1
         MODE_SPEED = 1
         DSI_VC_CTRL_n (n > 0)
         MODE = 0
         SOURCE = 0
         MODE_SPEED = 1

    DSI_PHY

    •   DSI_PHY_REGISTER0     (spec ; min ; max) in ns
         REG_THSPREPARE = 30   (76 ; 49 ; 80)
         REG_THSPRPR_THSZERO = 72   (181 ; 159 ; 188)
         REG_THSTRAIL = 29   (73 ; 72 ; 76)
         REG_THSEXIT = 58   (146 ; 106 ; 148)
    •   DSI_PHY_REGISTER1
         REG_TLPXBY2 = 11   (28 ; 30 ; 37)
         REG_TCLKTRAIL = 26   (66 ; 75 ; 79)
         REG_TCLKZERO = 106   (266 ; 296 ; 293)
    •   DSI_PHY_REGISTER2
         REG_TCLKPREPARE = 26   (66 ; 41 ; 71)

    DSIn_PLLCTRL

    •   DSI_PLL_CONFIGURATION1
         M5_CLOCK_DIV = 8  +1 for encoded value
         M4_CLOCK_DIV = 8  +1 for encoded value
         PLL_REGM = 333
         PLL_REGN = 15

    DISPC

    •   DISPC_CONTROLn
         STALLMODE = 1
         TFTDATALINES = 2
    •   DISPC_DIVISORn
         LCD = 1
         PCD = 2
    •   DISPC_SIZE_LCDn
         LPP = 479  +1 for encoded value
         DELTA_LPP = 0
         PPL = 319  +1 for encoded value

    It does not specificy the triggering mechanism (TE auto or manual).

    I hope it helps,

    Thanks
    Erwan

     

     

  • Hi William

    I've made three changes to the last configuration you posted. Could you please try with them?

    .pixel_clock  = 9712, 
     .regm  = 65
    .pck_div = 8, 

    Actually Erwan has a very good point. The panel is a manual update (command mode) panel.

    The only problem is that it is 1Lane,  not 2 Lanes and (please correct me if I am wrong) William choose RGB 16 bit due to a mismatch in the color format between OMAP and the LCD.

    Regards

    Rafael

  • Hi William, Rafael

    Could you explain the rational for chosing 1DL and RGB16 instead of 2DL and RGB18.

    Could you give a status of panel and DSI output behavior if you are able to probe DSI lanes,

    Thanks

    Erwan

     

  • Hi Erwan

    I do not have the details for the selection of 16 bit color, and I agree with you that 18 bit color should be tried.

    But the 1 Data lane limit is from the datasheet on the first post.

    Regards

    Rafael

  • Hi Rafael

    We met some problem when we use 18 bit color output.

    The color is not correct here.(But Full color is correct, EX: Red  Blue Green  Black  White).

    So we want to try 16 bit color here.

    Could you give me some suggestion about this situation?

    thank you.

  • Cool !! Congratulations !!

    But with so many settings posted here I do not know which one worked for you. Can you please post the settings that worked for you? 

    In the end, Is your panel working on command or video mode?

    Please put a register dump of the DISPC GFX related registers only. I think the problem lies there. Do not paste all the register dumps.

    Regards

    Rafael

  • Hi Rafael

    pixel_size = 18

    here is my settings.

    dsi_video_mode_enable(dssdev, 0x2e)

    static struct omap_dss_device panda4460_lcd_device = {
     .name   = "lcd",
     .driver_name  = "ili9486_dsi",
     .type   = OMAP_DISPLAY_TYPE_DSI,
     .data   = &dsi1_panel_data,
     .phy.dsi  = {
      .type = OMAP_DSS_DSI_TYPE_VIDEO_MODE,
      .clk_lane = 1,
      .clk_pol = 0,
      .data1_lane = 2,
      .data1_pol = 0,
     },
      
     .clocks = {
      .dispc = {
       .channel = {


        .lck_div = 1, /* LCD */// Logic clk 120MHz
        .pck_div = 12, /* PCD */ //10MHz
     
        .lcd_clk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
       },
       .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK,
      },

      .dsi = {
      
       .regn  = 16, /* DSI_PLL_REGN */  //Fint 2.4 MHz
     
       .regm  =150, /* DSI_PLL_REGM */ // DDR Clock 720MHZ  One Lane speed  = 360MHZ
     
       .regm_dispc =6, /* PLL_CLK1 (M4) *///PLL1 120MHz   
       .regm_dsi = 6, /* PLL_CLK2 (M5) *///PLL2 120MHz
     
       .lp_clk_div = 10, 
     
       .dsi_fclk_src   = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,
      },
     },
     .channel  = OMAP_DSS_CHANNEL_LCD,

    };

  • HI~~

    I have change the video mode to command mode.

    Seems like panel initial okay.

    But haven't pixel data (HS data) output on scope.

    Am I setting wrong ?

    static struct omap_dss_device panda4460_lcd_device = {
     .name   = "lcd",
     .driver_name  = "ili9486_dsi",
     .type   = OMAP_DISPLAY_TYPE_DSI,
     .data   = &dsi1_panel_data,
     .phy.dsi  = {
      .type = OMAP_DSS_DSI_TYPE_CMD_MODE,
      .clk_lane = 1,
      .clk_pol = 0,
      .data1_lane = 2,
      .data1_pol = 0,

     },
      
     .clocks = {
      .dispc = {
       .channel = {


        .lck_div = 1, /* LCD */// Logic clk 120MHz
                                   .pck_div =10, /* PCD */ //12MHz
     
        .lcd_clk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
       },
       .dispc_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
      },

      .dsi = {
     


       .regn  = 16, /* DSI_PLL_REGN */  //Fint 2.4MHz
     
       .regm  =150, /* DSI_PLL_REGM */ // DDR clock 720MHz ; One lane 360MHz
     
       .regm_dispc =6, /* PLL_CLK1 (M4) *///PLL1 120MHz
     
       .regm_dsi = 6, /* PLL_CLK2 (M5) *///PLL2 120MHz
     
       .lp_clk_div = 9, 

       .offset_ddr_clk = 0,
     
       .dsi_fclk_src   = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,
      },
     },
     .channel  = OMAP_DSS_CHANNEL_LCD,
     .skip_init = false,
     .platform_enable = NULL,
     .platform_disable = NULL,
       
    };

     

     

    panel driver code :

     

     r = omapdss_dsi_display_enable(dssdev);
     if (r) {
      dev_err(&dssdev->dev, "failed to enable DSI\n");
      goto err0;
     }


     taal_hw_reset(dssdev);

     omapdss_dsi_vc_enable_hs(dssdev, td->channel, false);

     r = ili9486_config(dssdev); // ILI9486 setting , corret on video mode
     

     td->enabled = 1;

     omapdss_dsi_vc_enable_hs(dssdev, td->channel, true);

     

     

     

    cat /sys/bus/omapdss/drivers/ili9486_dsi/display2/hw_revision

     

     Register setting below here


    =============== cat d/omapdss/clk    =================================
    - DSS -
    dpll4_ck 1536000000
    DSS_FCK (DSS_FCLK) = 1536000000 / 9  = 170666666
    - DISPC -
    dispc fclk source = DSI_PLL_HSDIV_DISPC (PLL1_CLK1)
    fck  120000000      
    - DISPC-CORE-CLK -
    lck  120000000       lck div 1
    - LCD1 -
    lcd1_clk source = DSI_PLL_HSDIV_DISPC (PLL1_CLK1)
    lck  120000000       lck div 1
    pck  12000000        pck div 10
    - LCD2 -
    lcd2_clk source = DSS_FCK (DSS_FCLK)
    lck  42666666        lck div 4
    pck  42666666        pck div 1
    - DSI1 PLL -
    dsi pll source = dss_sys_clk
    Fint  2400000         regn 16
    CLKIN4DDR 720000000       regm 150
    DSI_PLL_HSDIV_DISPC (PLL1_CLK1) 120000000       regm_dispc 6 (on)
    DSI_PLL_HSDIV_DSI (PLL1_CLK2) 120000000       regm_dsi 6 (on)
    - DSI1 -
    dsi fclk source = DSI_PLL_HSDIV_DSI (PLL1_CLK2)
    DSI_FCLK 120000000
    DDR_CLK  180000000
    TxByteClkHS 45000000
    LP_CLK  6666666
    ======================  d/omapdss/dispc =====================================                                         
    DISPC_REVISION                                     00000040
    DISPC_SYSCONFIG                                    00002015
    DISPC_SYSSTATUS                                    00000001
    DISPC_IRQSTATUS                                    00000000
    DISPC_IRQENABLE                                    0016d64f
    DISPC_CONTROL                                      00018b08
    DISPC_CONFIG                                       00030004
    DISPC_CAPABLE                                      00000000
    DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD)          00000000
    DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT)        00000000
    DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD)            00000000
    DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT)          00000000
    DISPC_LINE_STATUS                                  00000000
    DISPC_LINE_NUMBER                                  00000000
    DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD)               00000000
    DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD)               00000000
    DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD)               00000000
    DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD)               0001000a
    DISPC_GLOBAL_ALPHA                                 ffffffff
    DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT)             00000000
    DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD)               01df013f
    DISPC_CONTROL2                                     00000000
    DISPC_CONFIG2                                      00000000
    DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2)         00000000
    DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2)           00000000
    DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD2)              00000000
    DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD2)              00000000
    DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD2)              00000000
    DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD2)              00040001
    DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD2)              00000000
    DISPC_OVL_BA0(OMAP_DSS_GFX)                        bd096000
    DISPC_OVL_BA1(OMAP_DSS_GFX)                        bd096000
    DISPC_OVL_POSITION(OMAP_DSS_GFX)                   00000000
    DISPC_OVL_SIZE(OMAP_DSS_GFX)                       01df013f
    DISPC_OVL_ATTRIBUTES(OMAP_DSS_GFX)                 02000099
    DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_GFX)             04ff0138
    DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_GFX)           00000500
    DISPC_OVL_ROW_INC(OMAP_DSS_GFX)                    00000001
    DISPC_OVL_PIXEL_INC(OMAP_DSS_GFX)                  00000001
    DISPC_OVL_WINDOW_SKIP(OMAP_DSS_GFX)                00000000
    DISPC_OVL_TABLE_BA(OMAP_DSS_GFX)                   00000000
    DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD)            00000000
    DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD)            00000000
    DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD)            00000000
    DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD)             00000000
    DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD)             00000000
    DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD)             00000000
    DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2)           00000000
    DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2)           00000000
    DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2)           00000000
    DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2)            00000000
    DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2)            00000000
    DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2)            00000000
    DISPC_OVL_PRELOAD(OMAP_DSS_GFX)                    000004ff
    DISPC_OVL_BA0(o)                                   00000000
    DISPC_OVL_BA1(o)                                   00000000
    DISPC_OVL_POSITION(o)                              00000000
    DISPC_OVL_SIZE(o)                                  00000000
    DISPC_OVL_ATTRIBUTES(o)                            00008400
    DISPC_OVL_FIFO_THRESHOLD(o)                        07ff07f8
    DISPC_OVL_FIFO_SIZE_STATUS(o)                      00000800
    DISPC_OVL_ROW_INC(o)                               00000001
    DISPC_OVL_PIXEL_INC(o)                             00000001
    DISPC_OVL_FIR(o)                                   04000400
    DISPC_OVL_PICTURE_SIZE(o)                          00000000
    DISPC_OVL_ACCU0(o)                                 00000000
    DISPC_OVL_ACCU1(o)                                 00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_BA0_UV(o)                                00000000
    DISPC_OVL_BA1_UV(o)                                00000000
    DISPC_OVL_FIR2(o)                                  04000400
    DISPC_OVL_ACCU2_0(o)                               00000000
    DISPC_OVL_ACCU2_1(o)                               00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_ATTRIBUTES2(o)                           00000000
    DISPC_OVL_PRELOAD(o)                               00000100
    DISPC_OVL_BA0(o)                                   00000000
    DISPC_OVL_BA1(o)                                   00000000
    DISPC_OVL_POSITION(o)                              00000000
    DISPC_OVL_SIZE(o)                                  00000000
    DISPC_OVL_ATTRIBUTES(o)                            00008400
    DISPC_OVL_FIFO_THRESHOLD(o)                        07ff07f8
    DISPC_OVL_FIFO_SIZE_STATUS(o)                      00000800
    DISPC_OVL_ROW_INC(o)                               00000001
    DISPC_OVL_PIXEL_INC(o)                             00000001
    DISPC_OVL_FIR(o)                                   04000400
    DISPC_OVL_PICTURE_SIZE(o)                          00000000
    DISPC_OVL_ACCU0(o)                                 00000000
    DISPC_OVL_ACCU1(o)                                 00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_BA0_UV(o)                                00000000
    DISPC_OVL_BA1_UV(o)                                00000000
    DISPC_OVL_FIR2(o)                                  04000400
    DISPC_OVL_ACCU2_0(o)                               00000000
    DISPC_OVL_ACCU2_1(o)                               00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_ATTRIBUTES2(o)                           00000000
    DISPC_OVL_PRELOAD(o)                               00000100
    DISPC_OVL_BA0(o)                                   00000000
    DISPC_OVL_BA1(o)                                   00000000
    DISPC_OVL_POSITION(o)                              00000000
    DISPC_OVL_SIZE(o)                                  00000000
    DISPC_OVL_ATTRIBUTES(o)                            00008400
    DISPC_OVL_FIFO_THRESHOLD(o)                        07ff07f8
    DISPC_OVL_FIFO_SIZE_STATUS(o)                      00000800
    DISPC_OVL_ROW_INC(o)                               00000001
    DISPC_OVL_PIXEL_INC(o)                             00000001
    DISPC_OVL_FIR(o)                                   04000400
    DISPC_OVL_PICTURE_SIZE(o)                          00000000
    DISPC_OVL_ACCU0(o)                                 00000000
    DISPC_OVL_ACCU1(o)                                 00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_BA0_UV(o)                                00000000
    DISPC_OVL_BA1_UV(o)                                00000000
    DISPC_OVL_FIR2(o)                                  04000400
    DISPC_OVL_ACCU2_0(o)                               00000000
    DISPC_OVL_ACCU2_1(o)                               00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_ATTRIBUTES2(o)                           00000000
    DISPC_OVL_PRELOAD(o)                               00000100

        
    ================== cat d/omapdss/dsi1_regs ==========================
                                          
    DSI_REVISION                        00000030
    DSI_SYSCONFIG                       00000011
    DSI_SYSSTATUS                       00000001
    DSI_IRQSTATUS                       00010000
    DSI_IRQENABLE                       0014c000
    DSI_CTRL                            0008609f
    DSI_COMPLEXIO_CFG1                  6a000021
    DSI_COMPLEXIO_IRQ_STATUS            00000000
    DSI_COMPLEXIO_IRQ_ENABLE            3ff07fff
    DSI_CLK_CTRL                        a0346009
    DSI_TIMING1                         7fff1000
    DSI_TIMING2                         ffffffff
    DSI_VM_TIMING1                      00000000
    DSI_VM_TIMING2                      00000000
    DSI_VM_TIMING3                      00000000
    DSI_CLK_TIMING                      00001712
    DSI_TX_FIFO_VC_SIZE                 13121110
    DSI_RX_FIFO_VC_SIZE                 13121110
    DSI_COMPLEXIO_CFG2                  00030000
    DSI_RX_FIFO_VC_FULLNESS             00000000
    DSI_VM_TIMING4                      00000000
    DSI_TX_FIFO_VC_EMPTINESS            1f1f1f18
    DSI_VM_TIMING5                      00000000
    DSI_VM_TIMING6                      00000000
    DSI_VM_TIMING7                      000e0010
    DSI_STOPCLK_TIMING                  00000080
    DSI_VC_CTRL(0)                      60808fa3
    DSI_VC_TE(0)                        00000000
    DSI_VC_LONG_PACKET_HEADER(0)        00000000
    DSI_VC_LONG_PACKET_PAYLOAD(0)       00000000
    DSI_VC_SHORT_PACKET_HEADER(0)       00000000
    DSI_VC_IRQSTATUS(0)                 00000024
    DSI_VC_IRQENABLE(0)                 000000db
    DSI_VC_CTRL(1)                      20808d81
    DSI_VC_TE(1)                        00000000
    DSI_VC_LONG_PACKET_HEADER(1)        00000000
    DSI_VC_LONG_PACKET_PAYLOAD(1)       00000000
    DSI_VC_SHORT_PACKET_HEADER(1)       00000000
    DSI_VC_IRQSTATUS(1)                 00000000
    DSI_VC_IRQENABLE(1)                 000000db
    DSI_VC_CTRL(2)                      20808d81
    DSI_VC_TE(2)                        00000000
    DSI_VC_LONG_PACKET_HEADER(2)        00000000
    DSI_VC_LONG_PACKET_PAYLOAD(2)       00000000
    DSI_VC_SHORT_PACKET_HEADER(2)       00000000
    DSI_VC_IRQSTATUS(2)                 00000000
    DSI_VC_IRQENABLE(2)                 000000db
    DSI_VC_CTRL(3)                      20808d81
    DSI_VC_TE(3)                        00000000
    DSI_VC_LONG_PACKET_HEADER(3)        00000000
    DSI_VC_LONG_PACKET_PAYLOAD(3)       00000000
    DSI_VC_SHORT_PACKET_HEADER(3)       00000000
    DSI_VC_IRQSTATUS(3)                 00000000
    DSI_VC_IRQENABLE(3)                 000000db
    DSI_DSIPHY_CFG0                     0f22101b
    DSI_DSIPHY_CFG1                     42050d2f
    DSI_DSIPHY_CFG2                     b800000c
    DSI_DSIPHY_CFG5                     e3000000
    DSI_PLL_CONTROL                     00000000
    DSI_PLL_STATUS                      00000383
    DSI_PLL_GO                          00000000
    DSI_PLL_CONFIGURATION1              14a12c1f
    DSI_PLL_CONFIGURATION2              00656008

     

  • Hi Rafael,

    We used omap4460 in our design,we want to output 1280x800P60(VESA standards),from CSI1 port,how to configure panel timings?

        We use JR_4AI-1.4-P1_OMAP4460,board-44xx-tablet-panel.c

    static struct omap_dss_device tablet_lcd_device = {
     .name                   = "lcd",
     .driver_name            = "tc358765",
     .type                   = OMAP_DISPLAY_TYPE_DSI,
     .data   = &tablet_dsi_panel,
     .phy.dsi                = {
      .clk_lane       = 3,
      .clk_pol        = 0,
      .data1_lane     = 1,
      .data1_pol      = 0,
      .data2_lane     = 2,
      .data2_pol      = 0,
      .data3_lane     = 4,
      .data3_pol      = 0,
      .data4_lane     = 5,
      .data4_pol      = 0,

      .type = OMAP_DSS_DSI_TYPE_VIDEO_MODE,
     },

     .clocks = {
      .dispc = {
        .channel = {
        .lck_div        = 1,
        .pck_div        = 2,
        .lcd_clk_src    = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
       },
       .dispc_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
      },

      .dsi = {
       .regn           = 38,
       .regm           = 441,
       .regm_dispc     = 6,
       .regm_dsi       = 9,
       .lp_clk_div     = 5,
       .offset_ddr_clk = 0,
       .dsi_fclk_src   = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,
      },
     },

     .panel = {
      .timings = {
       .x_res  = 1280,
       .y_res  = 800,
       .pixel_clock = 65183,
       .hfp  = 10,
       .hsw  = 20,
       .hbp  = 10,
       .vfp  = 4,
       .vsw  = 4,
       .vbp  = 4,
      },
     },

     .ctrl = {
      .pixel_size = 24,
     },

     .reset_gpio     = 102,
     .channel = OMAP_DSS_CHANNEL_LCD,
     .skip_init = false,

     .platform_enable = NULL,
     .platform_disable = NULL,
    };

      

    Regards

    zengxing

  • Hi Wu

    I need to check the timings, but a command mode driver (in you case ili9486_dsi) must implement the update function.

    You  can check drivers/video/omap2/displays/panel-taal.c which is a command mode panel used on the blaze. Check the taal_update() function as a reference.

    Zengxing.

    I replied on another post you made. Regards.


    Regards

    Rafael 

  • Hi~ Rafael

     

    I have copy update funciton from taal driver,

    Should we need to change any settings here?

    updata function have beed run on runtime.

    But seems like pixel data haven't output on pandaboard.

  • Dear Rafael

    I found a cool thing~~

    When We use the settings 

    The 24 bit loosely pixel color format  output okay~~

    But have a blue line on panel.

    Could we fix this problem here?

    thank you.

    // =================Original  ====================

    //r = FLD_MOD(r, hbp-1, 11, 0); /* HBP */
    //r = FLD_MOD(r, hfp-1, 23, 12); /* HFP */
    //r = FLD_MOD(r, hsa-1, 31, 24); /* HSA */

    //r = FLD_MOD(r, tl-1 , 31, 16);

    // ================ After =====================


    r = FLD_MOD(r, hbp, 11, 0); /* HBP */
    r = FLD_MOD(r, hfp, 23, 12); /* HFP */
    r = FLD_MOD(r, hsa, 31, 24); /* HSA */

    r = FLD_MOD(r, tl , 31, 16);

  • Excellent news Wu.

     Congratulations.

    Yes, That has changed. Please check the following patch.

    http://review.omapzoom.org/#/c/16063/

    Could you share your final settings for the community?

    Thanks.

  • Rafael, Wu

    Again as i mention in previous post,  the H and V blanking parameters, on both DSI and DISPC, side and also the TL are only applicable in video mode and have no impact in command mode as DISPC works in stall mode.

    Are you sure your PPL and TE_size are correctly set.

    Thanks

    Erwan

     

     

  • Dear Erwan

    I haven't describe clear.

    This is still Video mode setting

    (Because Command mode haven't display frame now , We need to verify some thing here.)

     .phy.dsi  = {
      .type = OMAP_DSS_DSI_TYPE_VIDEO_MODE,
      .clk_lane = 1,
      .clk_pol = 0,
      .data1_lane = 2,
      .data1_pol = 0,
     },

     

      .lck_div = 1, /* LCD */// Logic clk 120MHz
     

    .pck_div =10, /* PCD */ //12MHz

     .regn  = 16, /* DSI_PLL_REGN */  //Fint 2.4MHz
     .regm  =150, /* DSI_PLL_REGM */ // DDR clock 720MHz ; One lane 360MHz
     
     .regm_dispc =6, /* PLL_CLK1 (M4) *///PLL1 120MHz
     
     .regm_dsi = 6, /* PLL_CLK2 (M5) *///PLL2 120MHz
     
     .lp_clk_div = 8, /* LPDIV */ // LP 7.5MHz

     

  • Hi Wu,
    Would you please give me board-omap4panda.c and panel-taal.c files ?
    I also do something like what you had done.
    But I don't understand how to modify two files clearly.
    Thanks.