Hello,
I try to measure data transfer time from SDRAM to internal SRAM memory on a c64x simulator. My configuration is :
- C6414 big endian cycle accurate simulator with CPU Frequency=300Mhz, EMIF Frequency = 100Mhz (configured through the target configuration on CCS4)
- L2 cache is not activated and SDRAM is non cacheable
The EMIF is configured to interface to a 16bits wide SDRAM using the following GEL File content:
myEmifInit()
{
GEL_TextOut("GEL EmifInit\n");
#define EMIFA_GCTL 0x01800000
#define EMIFA_CE1 0x01800004
#define EMIFA_CE0 0x01800008
#define EMIFA_CE2 0x01800010
#define EMIFA_CE3 0x01800014
#define EMIFA_SDRAMCTL 0x01800018
#define EMIFA_SDRAMTIM 0x0180001c
#define EMIFA_SDRAMEXT 0x01800020
#define EMIFA_CE1SECCTL 0x01800044
#define EMIFA_CE0SECCTL 0x01800048
#define EMIFA_CE2SECCTL 0x01800050
#define EMIFA_CE3SECCTL 0x01800054
/* EMIFA => SDRAM 32Mbytes */
*(int*)EMIFA_GCTL = 0x000200A8; /* CLK6EN = 1 - EK1EN = 1 - NoHold = 1 */
*(int*)EMIFA_CE0 = 0x00000090; /* CECTL0 - 16bits wide SDRAM */
*(int*)EMIFA_SDRAMCTL = 0x63114000; /* 4 banks - 8192 raws - 512 elements/raws - Refresh = 1 - Init = 1 - TRCD = 1 - TRP = 1 TRC=4 */
*(int*)EMIFA_SDRAMTIM = 0x00000000;
*(int*)EMIFA_SDRAMEXT = 0x0004B4A6; /* CAS latency = 2 */
*(int*)EMIFA_CE0SECCTL = 0x00000000;
*(int*)EMIFA_CE1 = 0x00000000; /* not used */
*(int*)EMIFA_CE2 = 0x00000000; /* not used */
*(int*)EMIFA_CE3 = 0x00000000; /* not used */
*(int*)EMIFA_CE1SECCTL = 0x00000000; /* not used */
*(int*)EMIFA_CE2SECCTL = 0x00000000; /* not used */
*(int*)EMIFA_CE3SECCTL = 0x00000000; /* not used */
}
I use the CSL DAT module to run a DMA transfert of 4096byte from SDRAM (address 0x80000000 = CE0 of EMIFA). I measure the data transfer time using the clock() primitive. Here is my project source code:
#include <csl_dat.h>
#include <csl.h>
#include <time.h>
long long myValues[2048];
long long* mySDRAMvalues = 0;
unsigned int inclk = 0;
unsigned int outclk = 0;
unsigned int overhead = 0;
void datTest()
{
inclk = clock();
Uint32 id= DAT_copy((long long*)0x80000000,myValues,4096);
DAT_wait(id);
outclk = clock();
}
int main(void)
{
CSL_init();
inclk = clock();
outclk = clock();
overhead = (outclk - inclk);
DAT_open(DAT_CHAANY,DAT_PRI_HIGH,0);
datTest();
printf("ov=%d in=%d out=%d\n",overhead,inclk,outclk);
return(0);
}
When running this test (compiled with -O2), I get about 5000 cycles to perform the datTest.
With a CPU frequency of 300Mhz, I get (5000/300e6)=~16,66µs to transfert 4096bytes = 2048 16bits SDRAM transfers ===> 8,13e-9s per EMIF transfer.
Then I get a transfer data rate of around 120e6 transfers/s which is higher than the EMIF frequency 100 Mhz as if the EMIF was not correctly configured
If anyone has an idea of what could be wrong in my test or analysis.
Thanks in advance
Laurent POYART
