DM8148: Question on HDVPSS1/2 in ConnID

Dear Pavel,

I've seen the MConnID table at the end of chapter 8 of TRM

IIUC priority in DDR access is done by DMM, by configuring DMM_PEG_PRIO_0-1. Is this correct?

If so, to decode those register I need to know the initiator index of a given peripheral.. is there a way to know which initiator index is given, for example, to Cortex A8, HDVPSS and so on?

Best Regards and thanks in advance,

Andrea

Hi Andrea,

Yes, the priority for the access from initiators to the DDR controller is done by DMM, by configuring the DMM_PEG_PRIO_0-1 registers. Check DM814x TRM, section 6.2.1.1
Priority Extension Generator (PEG).

The DMM is a module aimed at managing various aspects of memory accesses such as initiator-indexed priority generation. DMM add initiator-based priority to any incoming requests. A Priority Extension Generator (PEG) , located inside the DMM, generate priorities required by the SDRAM DDR controller, note that these priorities are not used in the DMM.

The initiator is a node inside the DM814x device and is either a CPU, peripheral or DMA engine, which can be internal bus Master. Each initiator is identified by a ConnID (Connection ID). With a limit of only 16 ConnIDs, some of the Initiators are grouped together with same ConnID.

ConnID: Any transaction in the system interconnect is tagged by an in-band qualifier ConnID, which uniquely identifies the initiator at a given interconnect point. A ConnID is transmitted in band with the request.

The ConnID for Cortex-A8 is 0x0, for HDVPSS (display port 1) is 0x24, for HDVPSS (display port 2) is 0x25. For all ConnID values, check Table 1-179. ConnID Values, the 6-bit version.

Regards,

Pavel

Pavel,

thank you very much for your quick answer!

Table 1-179 is what I was looking for! I already find that before but I didn't properly understand the 4 vs 6 bit encoding.

I'm really am sorry that I cannot put the "verified answer" flag on your post, but it help me in my issue.

Thanks

Andrea

Pavel,

can you kindly provide a configuration example, in order to test the following features (DMM and DDR configs):

• Set to max the priority of video subsytem
• Set to min the ARM priority

Hi Alberto,

I am not aware for any configuration example available in our EZSDK or elsewhere.

But we have really good and detailed description here:

https://e2e.ti.com/support/dsp/davinci_digital_media_processors/int-dm81x/f/518/t/120671.aspx?Redirected=true

Check this thread with the attached pptx (DM8168_Performance.pptx - Bandwidth Management in DM816x). I think the info here is also related to the DM814x.

Regards,

Pavel

Hi Pavel,

concerning

Pavel Botev said:

But we have really good and detailed description here:

https://e2e.ti.com/support/dsp/davinci_digital_media_processors/int-dm81x/f/518/t/120671.aspx?Redirected=true

It seems that this wonderful and detailed description is only available for TI internals - would be great to have access as an ordinary mortal, too.

Thanks in advance,
Joern.

Hello,

We have similar discussion here:

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/221518/781898.aspx

Regards,

Pavel