Clock frequency settings for TMS320DA828

Rajaram

Would you please send me the GEL setting for the 384MHz CPU and 128MHz SDRAM? Also, when you say it partially works, what does it mean?

Thanks
David

2402.dskda830_dsp_384Mhz_128Mhz_New.gel

hi David,

Thanks for your response.
I have attached the gel file. Please note that we don't use sysclk3 and sysclk7 and comments in the gel files may not be relevant and we use only dsp in da828.
When I said partially work it meant that
1)On some boards our audio decoding application which was working properly for 300Mhz and 133Mhz(with 4.5 divider) had lot of noise
2)On some boards we were not even able to load the application through JTAG
3)On some boards we had exceptions like following:
/-------------------------------------------------------------
>A0=0xc0032944 A1=0x8
>A2=0x1 A3=0xc01d4cc0
>A4=0x2033c0 A5=0xffc52a60
>A6=0xc02f7550 A7=0x100
>A8=0xc01d4488 A9=0xc01d4f5b
>A10=0xc01d00ac A11=0xc0030804
>A12=0x1 A13=0x84
>A14=0x180 A15=0x0
>A16=0xfffff3f9 A17=0xfffff91d
>A18=0x8a0 A19=0x6
>A20=0x7c7fc40 A21=0x7
>A22=0xf6ce0000 A23=0xf6a3c000
>A24=0xc01d2bb8 A25=0xc01d2ba8
>A26=0x1c A27=0xc02fc038
>A28=0xe A29=0xffaf4800
>A30=0xa A31=0x8
>B0=0xc01d4488 B1=0x3
>B2=0x0 B3=0xc029a0ac
>B4=0xc01d4ca8 B5=0xfff69ef4
>B6=0x9a0e0000 B7=0xfffff134
>B8=0x974639 B9=0xfff907e1
>B10=0x0 B11=0x180
>B12=0xb B13=0xc01d0bf8
>B14=0xc030f020 B15=0xc01c83f8
>B16=0x14db17 B17=0xfffffbf6
>B18=0xc02f7538 B19=0xc02f7568
>B20=0xc02f7520 B21=0x220
>B22=0xfb92c000 B23=0xfa518000
>B24=0xffff7ea8 B25=0xffe362d8
>B26=0xf8468000 B27=0xf7fbc000
>B28=0x11ac000 B29=0xf28000
>B30=0xff B31=0xff
>NTSR=0x1420d
>ITSR=0x20d
>IRP=0xc02e08f8
>SSR=0x0
>AMR=0x0
>RILC=0x10
>ILC=0x8
>Exception at 0xc02b3c8e
>EFR=0x2 NRP=0xc02b3c8e
>Internal exception: IERR=0x10
>Resource conflict exception
>ti.sysbios.family.c64p.Exception: line 248: E_exceptionMin: pc = 0xc02e08f8, sp = 0xc01c83f8.
>xdc.runtime.Error.raise: terminating execution
/-------------------------------------------------------------

Thanks and Regards,
Rajaram

Rajaram

In the GEL file, besides the PLL configuration change, there are other changes as well. Did these changes happen when you change the clock frequency?

When the clock frequency changes, did you update the McASPs clock as well?

Thanks

David

Hi David,

Thanks for the response.

>In the GEL file, besides the PLL configuration change, there are other changes as well. Did these changes happen when you change the clock frequency?
Yes, we saw those changes on the register.

Regarding McASP
For the transmitting side of McASP we are using Auxclk(24Mhz) which is independent of CPU clock.
For the receiving side it receives the clock on the pins from external source.
So we did not change anything in McASP when we changed from 300Mhz to 384Mhz. Also kindly let us know if we need to change anything regarding McASP.

Thanks and Regards,
Rajaram

Rajaram

Did you make these changes when you are also changing the PLL configuration? I tried to change the PLL configuration to 384MHz and 128MHz on my EVM and it is able to pass the memory test. Can you take your GEL file, change only the PLL configuration and nothing else, and see if it works?

Thanks

David

1715.dskda830_dsp_300Mhz_133Mhz.gel

Hi David,

Thanks for the response.
Please find the attached gel file with 300Mhz CPU clock for which our application
works.Only difference in the previous gel file is the cpu clock(sysclk instead of 4.5 divider),EMIFB clock source and SDRAM
timing parameters.
Yes we have tried changing only pll configuration and our application still gives the same results.
Please let us know if we are configuring them in proper manner.

Thanks and Regards,
Rajaram

Hi David,

Thanks for responding and sorry for the delay in reply.

Yes,we are enabling all the cache in dsp.
While transmitting audio data, it is from SDRAM(our stream i/o buffers are in SDRAM)
We receive the data using McASP0 ,process it and send it  through McASP1 to another device in I2s format.Tx
and rx are happening at  the same time. We have not explicitly configured any DMA channel.But we are using hEdma handle created
by edma3init() of the edma3_lld_02_00_01_04 drv/sample. We are looking into the possibilities of not configuring EDMA3 properly while
we can also see that application works for 300Mhz clock.But thanks a lot for pointing out this.

For the boards which work, we tested for a short duration and they worked consistently for that duration. Boards which failed consistently failed .
Physically there is no difference between the working and non working boards.
Please let us know if we are missing anything.

Thanks and Regards,
Rajaram

Hi David,

Regarding DMA channels my analysis is following:
While creating the driver instance using PSP,depending on
rxDmaEventNumber and txDmaEventNumber the channel will be requested. Accordingly
EDMA driver will allocate the channel. EDMA events numbers are associated with
corresponding peripherals in Table 6-19 of TMS320DA828 Rev.C Datasheet.
So event#0 is associated with McASP0 receive,which is specified in soc.xs of PSP.
So it probably takes Channel#0.

Please let me know if the analysis is wrong.

Thanks and Regards,
Rajaram