C6678, TSIP clock

Avi,

Frame-sync can be generated internally. More information is in the TSIP User Guide (http://www.ti.com/lit/ug/sprugy4/sprugy4.pdf) under Chapter 3 Clocks, Frames, and Data.

The TSIP offers six data rate options. The data rate options are listed in Table 3-1 (of the User Guide) with some corresponding information.

You need to set the Recieve Control Register, Recieve Clock Source Register, Transmit Clock Source Regsiter, and the Transmit Control Register to set up the revieve/transmit clocks.

I do not know what you should do with the pins because I do not know what you want to do, but Chapter 6 has a great initilization example.

[   Please click on the Verify Anwser on the bottom of this post if I have answered your questions.   ]

As I said, I would prefer to use the internal version of the TSIP clock and frame-sync instead of having it generated externally.

In this case, I need to know whether to leave those pins floating/pulled-up/down. Can you please check it for me?

Thanks.

Avi,

If you want to set the registers I mentioned prior, then you set those bits you mentioned before.

If you want to use the internal TSIP, the TSIP offers six data rate options. The data rate options are listed in Table 3-1 (of the User Guide) with some corresponding information.

Thanks.

[   Please click on the Verify Anwser on the bottom of this post if I have answered your questions.   ]

Elush,

According to what I saw in sprugy4 Table3-4, I HAVE to choose between CLK_A or CLK_B. There's no "Internal" option at all !

Is this correct?

Avi,

Yes but the clock choices matter on what data rates you set.

The serial interface clock frequency can be either 16.384 MHz (default) or 8.192 MHz. The data rate for the serial interface links can also be set to 16.384 Mbps or 32.768 Mbps. The maximum number of active serial links is reduced to four and two, respectively, in these configurations.The serial interface clock frequency can be either 32.768 MHz or 16.384 MHz for 16.384 Mbps serial links, and 65.536 MHz or 32.768 MHz for 32.768 Mbps serial links. Maximum occupation of the serial interface links for the entire TSIP is 1024 transmit and receive timeslots in all configurations, which shows in Table 3-1 what you should do to those pins depending on the 4 different clock options you want to choose from.

[Please click on the Verify Anwser on the bottom of this post if I have answered your questions.]

Elush,

I'm asking about clock source (!!!) and you answer about clock frequency and data rate...

I just wanted to know if I HAVE to supply the C6678 with a clock in pins CLKA0, CLKB0, FSA0 and FSB0 or is there a way to generate these clock signals inside one of the DSPs PLLs without the need to generate this clock on my board