Hi,I've run an IPC example on the simulator using IPCGR registers to notify each
core. In fact I make core0 trigger core1 then the core1 triggers core2, and so
on).I printed out the software simulation cycle which is about 500,000 during this
procedure: core0->core1->core2->core3->core0. However the same test running on
the 6678 evaluation board(frequency of 1Ghz) does not have the same result.I'll
cost about 0.5second(500,000,000 cycles) !!
1. Is there anyting wrong with my test?
2. If not,which is the most cycle-saving way to do multicore notification?
PS: I've tried to use a volatile global varible which is mapped in 2M shared memory to act as an notification trigger. Once one core modifies it ,other cores will know.The same procedure "core0->core1->core2->core3->core0" costs almost 0.5 second too.
