A Question about TMSC6678 Cache Coherence

CorePacA accessing CorePacB's local memories is treated as an External Memory Access.  Manual coherence operations would need to be used.  The C66x DSP Cache User Guide SPRUGY8, which can be found in the User Guide section of the TMS320C6678 product page, details how to handle external memory coherency.

Best Regards,

Chad

Hello，

     Thanks for your reply! Assume that CorePacA's  L1D cache and CorePacB's L1D have a same copy of L2 SRAM.If CorePacA modified the data in it's L1D cache,I have to maintain the coherence in my software so that the  CorePacB's L1D cache can have the right data.Is that right?Thanks!

Best Regards,

Levy

Where's the L2 reside?  The CorePac of the L2 will always maintain coherency with what is currently in that L2.  The other CorePac would need to perform Write Backs to the L2 after it attempts to modify that L2 space.  It will also need to perform Invalidates if that L2 was updated by the other core before reading.

Hi Chad,

are you sure this is true?

This is how I understand it:

If core A writes to the L2 of another core B, it uses the global L2 address of core B 0x1_800000. This address is not cached by A, unless it's mapped into a cached memory region. Even If core B now reads the value which core A just has written by using the local L2 address, there also should be no problem because the snoop-write mechanism of the cache controller automatically updates L1D of core B.

The same should be true if core A reads in L2 of core B. The global adress is not cached by A and the snoop coherence protocol makes sure that the data is valid.

In other words: no cache coherence operations are necessary when cores exchange data in L2.

What do you think?

Ralf

Ralf,

In this case since you are not enabling caching of the Core B's L2 global data space by Core A, then this is true. Note what I stated was also true, but assumes cache is enabled for accesses of those spaces.

Best Regards,

Chad

Accoding to the C66 corepac manual:

To support L1D cache coherence with respect to DMA/IDMA traffic in L2 RAM, the
L1D controller supports two cache coherence commands arriving from L2: snoop-read
(SNPR) and snoop-write (SNPW). The L2 only sends these snoop commands, when
necessary, in response to DMA and IDMA activity in L2 RAM.

So the documentation mentions only DMA/IDMA explicitly.
To find out wether L2 traffic induced by other masters also is covered, I guess writing a short code snippit would be the simplest way ;)

I would be interested to hear your findings =)

Regards, Clemens

Hello Clemens,

my observations are that the snoop-operations also work for L2 access by different cores.

I was also confused by the CorePac manual. Maybe someone can confirm this and update the CorePac manual.

Ralf

Hello Chad,

We are using 6670 DSP processor and are planning to use L2SRAM of Core3 as a shared region between core2 and core3. This region would be holding some data structures that are of interest  to both the cores. Before we proceed with this implementation, we have following queries

1. How to disable cache on this region for core2

2.If core2 modifies the contents of this region, will they be reflected on the cache of core3

3.If core3 modifies the contents in this region, will the contents be updated in the physical memory and its cache simultaneously.

Any other problems do you foresee in this approach. Your support would be well appreciated.

Regards,

Naveen

Naveen,

For cache register controls, please see the C66 CorePac UG and for Coherency please see the C66 DSP Cache User Guide both can be found in the User Guide section of the TMS320C6670 <-- Product Page.

Best Regards,
Chad

Hello Naveen,

1. Cache for the global L2 adresses should be turned off by default (I'm working with the C6678). To enable cache for the global L2 address range of core3, you can place the following lines into the .cfg script:
   var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');
   Cache.setMarMeta(0x13800000, 0x100000, Cache.PC | Cache.PCX | Cache.PFX);
2. If cache is disabled for the global adresses, modifications of L2 in core3 by an external master should be visible to core3, even if the data is already cached by core3's L1D (snoop coherence protocol).
3. The same should be true in the other direction.

Ralf