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6713 EMIF Problem when EMIF frequency greater then 50 MHz

Zeeshan Ansari
Prodigy 110 points

I am working on the Interface between EMIF of TMS320C6713 and FIFO created with in FPGA I write an array from EMIF using CE2 with in FIFO and Read back..

I have read that  EMIF is running on SYSCLK3 which can be set to maximum value of 100 MHz.

I am also using a Logic analyzer to monitor signals of EMIF on Logic analyzer.

When EMIF is running at frequency less then 50 MHz all signals are correct on Logic analyzer and in watch window correct data is shown. But when EMIF clock frequency increases more than 50 MHz data written on EMIF last (Last written word which I write on any CE2 or CE3) is read first on CE2 which is shown in watch window array, but on logic analyzer all signals are correct.

Kindly try to solve my problem as last written data is received first on EMIF when EMIF frequency in greaterr then 50MHz.

Regards,

Zeeshan

  • 0
    TI__Guru* 84110 points

    Zeeshan,

    When running the EMIF greater than 50MHz, how fast do you run it?

    Which configuration mode do you use for the interface with the FPGA? What timing parameters do you program?

    You will have to look at the EMIF signals with something like an oscilloscope to get higher timing resolution than with a logic analyzer. Some LAs have a scope mode with 2ns or tighter resolution which may help. But simply looking at the signals with single-sample-per-clock will not help you to confirm the timing results.

    You have a system that has to be debugged, meaning that the DSP code (1) writes through the EMIF bus (2) to the FPGA pins (3), then the FPGA stores the data (4), the reverse is then true when the DSP code (5) reads through the EMIF bus (6) from the FPGA pins (7) which requires the FPGA access logic to perform (8). Observation at all of the points will be required.

    You may take confidence that the C6713 will perform as you have programmed the EMIF to work and as your code directs the accesses. The most likely point of your problem is in the timing that occurs on the EMIF bus.

    Zeeshan Ansari said:
    when EMIF clock frequency increases more than 50 MHz data written on EMIF last (Last written word which I write on any CE2 or CE3) is read first on CE2 which is shown in watch window array, but on logic analyzer all signals are correct.

    This is difficult to understand what you are describing. But it seems that the DSP is reading data that the logic analyzer does not show existing on the bus. Is the LA a real LA or logic inside the FPGA?

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 110 points

    RandyP,

    I want to run EMIF at 90MHz.

    Asynchronous data interface is used.

    I am using both real LAs of Agilent and Chip Scope pro Logic inside FPGA.

    You understand correctly the problem "DSP is reading data that the logic analyzer does not show existing on the bus".

    Problem is due to high EMIF frquency below 50MHz EMIF run well.

    Regards,

    Zeeshan