sys_arch.c: /** * This function is used to lock access to critical sections when lwipopt.h * defines SYS_LIGHTWEIGHT_PROT. It disables interrupts and returns a value * indicating the interrupt enable state when the function entered. This * value must be passed back on the matching call to sys_arch_unprotect(). * * @return the interrupt level when the function was entered. */ sys_prot_t sys_arch_protect(void) { sys_prot_t status; status = (IntMasterStatusGet() & 0xFF); IntMasterIRQDisable(); return status; } interrupt.c: /** * \brief Returns the status of the interrupts FIQ and IRQ. * * \param None * * \return Status of interrupt as in CPSR. * * Note: This function call shall be done only in previleged mode of ARM **/ unsigned int IntMasterStatusGet(void) { return CPUIntStatus(); } cpu.c: /* ** ** Wrapper function for the IRQ status ** */ __asm(" .sect \".text:CPUIntStatus\"\n" " .clink\n" " .global CPUIntStatus\n" "CPUIntStatus:\n" " mrs r0, CPSR \n" " and r0, r0, #0xC0\n" " bx lr");
Since I think the "and" instruction is zero-extended to 32 bits, then I am not sure what the "& 0xFF" does in sys_arch_protect().
btw: the comment above CPUIntStatus() says "IRQ" when I think it should say "FIQ and IRQ".