• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 100 subscribers
  • Views 837 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

RX_HOST_ERR_ CODE field in CPDMA's DMASTATUS register indicates "SOP buffer length not greater than offset"

Delio Brignoli
Intellectual 675 points

Hello,

The CPDMA (on DM814x) halts with error code "SOP buffer length not greater than offset" (0x6) in the RX_HOST_ERR_ CODE field in CPDMA's DMASTATUS register. This occurs on the first packet received, on CPDMA channel 0x7. The Channel Head Descriptor Pointer (RX7_HDP) points to a valid CPPI RX descriptor. The descriptor fields hold correct values as far as I can see and the buffer length field (set to 1500 bytes decimal) is certainly greater then the buffer offset register RX_BUFFER_OFFSET which is set to 0. The error occurs before any data is written to the packet buffer pointed to by the descriptor. Frames with VLAN priority of 2 and 3 are mapped to CPDMA channel 0x7 by configuring the various PRI_MAP registers, all other traffic goes to channel 0x0. RX on CPDMA channel 0x0 works fine up to the moment the first packet is received on channel 0x7, at which point the CPDMA halts with the aforementioned error.

Is "SOP buffer length not greater than offset" set under conditions other than buf_len <= offset on SOP? Thanks.

Kind Regards
--
Delio Brignoli
AudioScience Inc

  • 0
    TI__Expert 8250 points

    Hi

    Can you clarify if the DMA descriptors are held in the embedded RAM(inside the IP) or placed in DDR memory.

    One possiblity for the error to show up would be if the CPDMA Descriptor update did not take effect (either did not reach memory because the write operation was a posted one or has been re-ordered) before the update to the head descriptor pointer. On Linux systems we could use the IO barrier instructions(dmb())  to avoid this situtation

    Do let me know if this  is seen consistently(everytime you initiate reception on channel 0x7) and whether the system load (memory transactions) is high when this happens

  • 0 in reply to Srirama Govindarajan
    Intellectual 675 points

    Hello Srirama,

    Thank you for helping with this. DMA descriptors are held in the embedded CPPI RAM. This problem occurs independently of system load and is triggered by the first packet received on DMA channel 0x7 (this happens on any channel not just channel 0x7). I can setup the RX DMA channel and the VLAN priority->RX channel mapping on CPSW and avoid sending frames destined to that channel for as long as I like and the CPDMA will continue to work fine. However when start sending frames with the priority associated to the RX channel the CPDMA locks up as I described on the first frame. All this should rule out the scenario you outlined, correct? I should mention I am able to transmit frames using channel 0x7 (or any other TX channel) just fine and that I am running my code under SYS/BIOS (6.33.00.19) on the C674x DSP core.

    Kind Regards
    --
    Delio Brignoli
    AudioScience Inc


  • 0 in reply to Delio Brignoli
    Intellectual 675 points

    Hello again Srirama,

    I have resolved the issue. I was writing an incorrect address of the buffer descriptor in the CPDMA Rx Head Descriptor Pointer register. The DSP and CPDMA have different base addresses for the CPPI RAM and I forgot to map from one to the other before writing to the HDP register.

    Kind Regards
    --
    Delio Brignoli
    AudioScience Inc

  • 0 in reply to Delio Brignoli
    TI__Intellectual 1070 points

    Hi Delio,

    I am glad you were able to resolve the issue, therefore I am going to close this thread since it has ben solved. 

    Thanks,

    Derek