TI Team,
I'm in the process of converting my L138 design into the AM1808. I have a few questions about clocking below:
1.Can the AM1808 24MHz clock (derived from the xtal oscillator) be buffered through pin T18?
[Lawrence] Yes, but note that we don’t spec specific timing characteristics (e.g. duty cycle, rise times) for this signal.
2.How do we configure the AM1808 registers to do this? I was unable to find Non-OS sample code that shows how to do this.
[Lawrence] The PLLC0 OBSCLK Select register (OCSEL) controls which clock is output on the CLKOUT pin. In the AM18x TRM, please see section “7.3.7 PLLC0 OBSCLK Select Register (OCSEL)” for a complete description. Also, I recommend “Figure 7-1 PLLC Structure” for a diagram showing this device’s clock structure including configuration for CLKOUT. Here is the link to the AM18x TRM on ti.com: http://www.ti.com/general/docs/litabsmultiplefilelist.tsp?literatureNumber=spruh82a
3.Can the 24MHz oscillator be trimmed by using a small trim capacitor?
[Lawrence] In the AM18x Datasheet, see section “5.5 Crystal Oscillator or External Clock Input” for recommendations and requirements. In general, C1 and C2 represent the total capacitance of the respective PCB trace, load capacitor, and other components (excluding the crystal) connected to each crystal terminal. The value of capacitors C1 and C2 should be selected to provide the total load capacitance, CL, specified by the crystal manufacturer.
I’d also add that it’s a good practice that your pre-production printed circuit board designs include two optional resistors Rbias and Rd in case they are required for proper oscillator operation when combined with production crystal circuit components. In most cases, Rbias is not required and Rd is a 0-Ω resistor. These resistors may be removed from production PCB designs after evaluating oscillator performance with production crystal circuit components installed on pre-production PCBs. I’ve attached a diagram showing Rbias and Rd, for reference.
Also, as a side note, in the AM18x Si Errata document, I recommend you refer to section “2.1.5 System-Level ESD Immunity Usage Note”, for additional considerations related to crystal design for this device.
Regards,
Lawrence
