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MCBSP - PDK_C6657_1.1.1.4 version - MultiChannel Mode option with External Clocks/Frame Syncs

Other Parts Discussed in Thread: TMDSEVM6657

Hi,

  I am using McBSP Driver code to make multichannel working. In this example application there is no multichannel. so I enable multichannel and am getting difficulty in trying to link "frmLen1" in Mcbsp_DataConfig to no.of timeslots enabled. 

/* ========================================================================== */
/* MACRO DEFINTIONS */
/* ========================================================================== */

#define NUM_BUFS 2 /* Max of 2 outstanding requests */
#define NUM_OF_CHANNELS 24 /* Number of slots to be used */
#define BUFSIZE (80*NUM_OF_CHANNELS) /* 1K of data transceive */

There is a definition of 

/**< settings to configure the TX or RX hardware sections */
Mcbsp_DataConfig mcbspChanConfig =
{
Mcbsp_Phase_SINGLE,
Mcbsp_WordLength_8,
Mcbsp_WordLength_8, /* Dont care for single phase*/
NUM_OF_CHANNELS,
NUM_OF_CHANNELS, // Only using single phase, hence num channels is 0
Mcbsp_FrmSync_DETECT,
Mcbsp_DataDelay_1_BIT,
Mcbsp_Compand_OFF_MSB_FIRST,
Mcbsp_BitReversal_DISABLE,
Mcbsp_IntMode_ON_SYNCERR,
Mcbsp_RxJust_RZF, /* Dont care for TX */
Mcbsp_DxEna_OFF
};

Mcbsp_ChanParams mcbspChanparamTx =
{
Mcbsp_WordLength_32, /* wordlength configured */
&loopJob[0], /* loop job buffer internal */
8, /* user loopjob length */
NULL, /* global error callback */
NULL, /* edma Handle */
1, /* EDMA event queue */
8, /* hwi number */
Mcbsp_BufferFormat_MULTISLOT_NON_INTERLEAVED,
TRUE, /* FIFO mode enabled */
&mcbspChanConfig, /* channel configuration */
&mcbspClkConfigTx, /* clock configuration */
&mcbspMultiChanCtrl, /* multi channel control */
0x00000003, /* 0,1 timeslots */
0x00,
0x00,
0x00
};

Mcbsp_ChanParams mcbspChanparamRx =
{
Mcbsp_WordLength_32, /* wordlength configured */
&loopJob[0], /* loop job buffer internal */
8, /* user loopjob length */
NULL, /* global error callback */
NULL, /* edma Handle */
2, /* EDMA event queue */
8, /* hwi number */
Mcbsp_BufferFormat_MULTISLOT_NON_INTERLEAVED,
TRUE, /* FIFO mode enabled */
&mcbspChanConfig, /* channel configuration */
&mcbspClkConfigRx, /* clock configuration */
&mcbspMultiChanCtrl, /* multi channel control */
0x00000003, /* 0,1 timeslots */
0x00,
0x00,
0x00
};

/**< clock setup for the TX section */
Mcbsp_ClkSetup mcbspClkConfigTx =
{
Mcbsp_FsClkMode_INTERNAL,
8000, /* 96KHz */
Mcbsp_TxRxClkMode_INTERNAL,
Mcbsp_FsPol_ACTIVE_HIGH,
Mcbsp_ClkPol_RISING_EDGE
};

/**< clock setup for the RX section */
Mcbsp_ClkSetup mcbspClkConfigRx =
{
..

8000, /* 96KHz */
...

};

So I need to set NUM_OF_CHANNELS as 24. But slots to be enabled only 2 in Multichannel control . 

But the buffer I am looking for is of size say  80 Frames (10 msecs) * 2 timeslots * wordlen (2bytes). 

If I change NUM_OF_CHANNELS to 2 since I enabled only TWO slots in Multichannel mode. The MCBSP fails to configure. 

Any suggestions as to how to modify the application or driver? 

Regards,

Hari

Note: My suggestion is to define NUM_OF_CHANNELS_IN_A_FRAME (total number of slots say ex: 24) to be assigned to frameLen1, .. 

to define the macro NUM_OF_CHANNELS (time slots enabled in a frame) in this example it is 2. 

Use this NUM_OF_CHANNELS for iobuf BUFSIZE calculation and use this macro in 

case Mcbsp_BufferFormat_MULTISLOT_NON_INTERLEAVED:
*aCnt = chanHandle->roundedWordWidth;
*bCnt = NUM_OF_CHANNELS; /*(uint16_t)(chanHandle->chanConfig.frmLen1 + chanHandle->chanConfig.frmLen2);*/
/* temp Size is always a multiple of the acnt hence the division *
* result will always be an integer */
*cCnt = (uint16_t)(tempSize /((*aCnt) * (*bCnt)));

>> Also we should not add both frmLen1 and frmLen2 here if it is not dual phase. 

  •  Hi,

      I fed  RCLK, XCLK, RFS and XFS to the EVM 80-pin Connector from an external source. I defined the MCBSP driver 

    /**< clock setup for the TX section */
    Mcbsp_ClkSetup mcbspClkConfigTx =
    {
    Mcbsp_FsClkMode_INTERNAL, //Mcbsp_FsClkMode_EXTERNAL
    8000, /* 96KHz */
    Mcbsp_TxRxClkMode_INTERNAL, //Mcbsp_TxRxClkMode_EXTERNAL
    Mcbsp_FsPol_ACTIVE_HIGH,
    Mcbsp_ClkPol_RISING_EDGE
    };

    /**< clock setup for the RX section */
    Mcbsp_ClkSetup mcbspClkConfigRx =
    {
    Mcbsp_FsClkMode_INTERNAL,
    8000, /* 96KHz */
    Mcbsp_TxRxClkMode_INTERNAL,
    Mcbsp_FsPol_ACTIVE_HIGH,
    Mcbsp_ClkPol_FALLING_EDGE
    };

    However I do not see MCBSP running. FPGA is written with decimal value 11 to disable FPGA to drive the MCBSP. 

    Did anyone try the EVB with External clocks/Framesyncs? Should we feed SCLK too? 

    It appears that Tx Does not begin. 

    Regards,

    Hari

  • MCBSP on External Clocks/Frame Syncs

    Board: TMDSEVM6657

    Alpha version. 

    We provided clocks on 80-pin connector:

       DSP_MCBSP0_RXCLK, TXCLK, FSR, FST from an external source of 2.048MHz Clock and 8.0 KHz frame Sync. 

    Then I am running the board with the modifications at:

    /**< clock setup for the TX section */
    Mcbsp_ClkSetup mcbspClkConfigTx =
    {
    Mcbsp_FsClkMode_EXTERNAL, //Mcbsp_FsClkMode_INTERNAL,
    8000, /* 96KHz */
    Mcbsp_TxRxClkMode_EXTERNAL, //Mcbsp_TxRxClkMode_INTERNAL,
    Mcbsp_FsPol_ACTIVE_HIGH,
    Mcbsp_ClkPol_RISING_EDGE
    };

    /**< clock setup for the RX section */
    Mcbsp_ClkSetup mcbspClkConfigRx =
    {
    Mcbsp_FsClkMode_EXTERNAL,
    8000, /* 96KHz */
    Mcbsp_TxRxClkMode_EXTERNAL,
    Mcbsp_FsPol_ACTIVE_HIGH,
    Mcbsp_ClkPol_FALLING_EDGE
    };

    MCBSP TX never Begins. I do not get edmaTxDone set. 

    Disabled DLB mode too. - Does not kick in. 

  • Can anyone help in getting the MCBSP to run with External Clocks/Frame Syncs source? 

    Regards,

    Hari