hi,
I am trying to transmit a packet using CPPI DMA in the response of a HOST. I have done the following initialization and settings in the same sequence, but nothing appears on USB bus, is there any thing i am missing or doing wrong way?
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Queue manager control setup
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1- Allocate memory for CPPI DMA memory region 0 = 1024*32 Bytes
2- Allocate memory for CPPI DMA link ram 0 = 1024*4 Bytes
3- stored the pointer of Link RAM 0 memory, Link RAM 0 size (1024), and memory region 0 pointer to the related registers
4- Memory region 0 control reg: desc_size= 0 (2^(5+0) = 32), reg_size = 5 (2^(5+5) = 1024), start_index=0 (as only one region is being used)
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CPPI control registers setup
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5- Tx Channel N Global Configuration Register (using N from 0-14 for 1-15 endpoints) = Just enabled the channels (0-14) by setting the most significant bit in related registers
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CPPI Scheduler configuration
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6- CPPI DMA Scheduler Table Word N = populated the table up to 8 words (30 entries (15 channels 0-15, each channel has 2 entries in one word that is one for TX and one for RX)). Values are shows as under for these 8 words programmed in this registers
SCHEDULE_WORD0 0x81018000
SCHEDULE_WORD1 0x83038202
SCHEDULE_WORD2 0x85058404
SCHEDULE_WORD3 0x87078606
SCHEDULE_WORD4 0x89098808
SCHEDULE_WORD5 0x8B0B8A0A
SCHEDULE_WORD6 0x8D0D8C0C
SCHEDULE_WORD7 0x00008E0E
7- CPPI DMA Scheduler Control Register = Enabled schedular by setting the MSB and also programmed the 30 as number of entries
8- USBSS IRQ_ENABLE_SET = enabled tx_pkt_cmp_0 and rx_pkt_cmp_0 interrupts
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When any endpoint is configured 1st time except EP0
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9- when EP0-EP1 is configured 1st time for usage at that time a 32 bit aligned memory is allocated of 32 bytes for each descriptor for 1024 descriptors (1024 * 32 bytes). This is to store the descriptors we create for this EP.
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While transmitting from a EP except 0 using CPPI DMA
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10- Clear Global RNDIS bit using USB0CTRL register
11- Set requested EP DMA Transparent mode using USB0TXMODE register
12- Required number of descriptors (1 PD and all others BD) are created and filled according to the following, each descriptor is 32 bytes log (8 words).
word0 :: Descriptor type=16, Protocol-specific valid word count=0, Packet length= total data length to be transferred (for BD this reg is written as 0 on all bits)
word1 :: Written the full register with 0
word2 :: type of this packet = 5, On-chip=0, Packet return queue # = set accordingly, (for BD type of this packet is not present )
word3 :: Buffer 0 length = current data length to be transferred in this packet
word4 :: Buffer 0 pointer = address of memory where data to be transmitted is placed
word5 :: Next descriptor pointer = pointer to next descripter
word6 :: Original buffer 0 length = same as Buffer 0 length
word7 :: Original buffer 0 pointer = same as Buffer 0 pointer
13- Pushed all of above created descriptors (PD 1st then other BDs in the sequence) on by one by writing "Queue N Register D" using corresponding Queue number of USB0 Tx Endpoint x (x is 1-15), using the 1st queue of all these 15
-a- desc_ptr = the PD memory address (remember it is 32 bit aligned so last 5 bits will be zero so assuming that controller will append these 5 zeros to make it complete address)
-b- desc_size = 2 ( as descriptor size is 32, so 0=24, 1=28, 2=32, -----)
14- To Enable DMA need to set these 2 things in CSR: -a- Clear Autoset -b- Set DMAReqEnab & DMAReqMode
Waiting for the response. Thank you in advance.
