Does anyone know if video capture only happens when CAPEN is high or whether a rising edge on CAPEN causes a block of pixels to be acquired? This is for 16-bit raw capture on a DM648.
Our application is entirely bespoke and the image is passed over from an FPGA on the video port interface at a fairly slow rate (around 1 fps). We want to increase image throughput at our processing stage by braking up the image block into sub frames. At the moment we use CAPEN to span an entire frame which gets passed into our processing buffer. We want to break the CAPEN into about 1/8th of a frame and think this may be possible using single rising edge pulses to trigger a block of pixels to be acquired. We already use data contained within the initial line to indicate frame start information so synchronisation wouldn't be a problem. The system is real time so we don't want to interrupt the pixel capture in this transfer.
Are there any video capture timing diagrams available for the DM648 that show the raw capture mode?
I have been reading the SPRUEM1B Video Port Users Guide but this only seems to show timing diagrams for the display modes. I also note that section 3.7 indicates that "...the data is sampled by the interface only when the CAPEN signal is active", however we suspect that this is not true all of the time.
Thanks
Paul Kushner
