Can't access CNTFRQ register

Any ideas?

Thanks....

Hi John,

The CNTFRQ register is part of system timer, and this is not part of Cortex-A8 core I think. So, that operation is invalid.

And, coming to the actual problem that, in the DMTimer example the ISR is triggered every 2-3 seconds instead of .7 seconds,

Have you done any modification to the existing example ? which platform are you testing ?

Regards,

Sujith.

Hi Sujith,

                The CNTFRQ is actually part of the Cortex-A8 and should be accessible as long as your are running in supervisor mode (is there something different about getting to the register in the AM3359?). We are using the Critical Link MityArm development board which also uses a 24M oscillator (same as Beaglebone.) We allow the Linux Uboot to bring up the card and then load StarterWare instead of the kernel. I have not changed any of the DMTimer programming (it is using the CLK_M_OSC for the timers.) I just trying to verify what the ARM actually thinks is the system frequency is, hence trying to look at the CNTFRQ register. The DMTimer examples use an up count of 0xffffff before a rollover is supposed to trigger the isr:

  0xffffff = 16, 777, 215 ==> 1/24Mhz * 16, 777, 215 = .698938 seconds ~ .7 seconds

Is there some other way to try to verify the AM3359 DMTimers clocking?

Thanks,

     John C.

Hi John,

I dont see the Generic Timer (and hence CNTFRQ register) in Cortex-A8 TRM. May be the difference lies between StarterWare bootloader and the one you are using in some PLL configs.. You can probably check for the same. I think there is no pin-out  of Timer input clock.

Regards,

Sujith.

Hi Sujith,

               I will admit that you will not find mention of the register in the TRM, but the ARM (Architecture Reference Manual) for the ARMv7-A and ARMv7-R does mention it, so I assume that it is in the core. The u-boot code uses the same type of assembly instruction to access the CSSELR (Cache Size Selection Register) which is another register not in the TRM.

    /* Write to Cache Size Selection Register(CSSELR) */
    asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));

     This clip of code was from a u-boot file cache_v7.c written by Aneesh V at TI. All of these registers seem to revolve around the p15 reference in the assembly, but even in Arch. reference manual they never have a summarized list of what is available. According to manual the CNTFRQ is supposed to be programmed early on in boot. Is the source code available for the StarterWare bootloader on the beaglebone ?

Thanks,

     John C.

Sujith,

         Well that would explain why the processor aborts. It has definable been a frustrating part of working with the ARM processors in that the ARM documents don't have something like a summary table that shows which Cortex variations have which components. The ARM document does not even have the word Cortex in it. The Cortex-A8 link below will lead you to the Architecture document that I have been using.

http://www.arm.com/products/processors/cortex-a/cortex-a8.php

Can you tell me where you found out that the A8 does not have the generic timer? If it is not in the A8, then the Architecture document should at least have some mention of reference another document about specific implementations.

Thanks,

     John Conover

Hi John,

I dont know whether anywhere it is mentioned that "Generic timer is not part of Cortex-A8". But what I see normally is, the TRM of a particular implementation contains the features supported by that core. This may not be in detail. For the details, we need to refer to the corresponding architecture version's ARM Architecture Reference Manual.

Regards,

Sujith.