EMIFA Data Bus Parking timings

Hi TI,

Any comments on this? 

Well, now there's a a kind of clarification in the new revision of C6745 TRM (SPRUH91B):

"The data bus is released (tri-stated) when the chip enable (EMA_CS[n]) is asserted by EMIFA for the read access. After the read operation is completed, the data bus is driven again by the bus parking feature at the end of the turnaround time."

But unfortunately there's no data again in DS (SPRS377E) for EMA_D[15:0] 3-stated/driving timings in the EMIFA Asynchronous Memory Switching Characteristics (Table 5-23).

Moreover, it is still unclear whether the data bus is released in Select Strobe mode at the start of setup period as it shown in Figure 18-12 of TRM  or at the start of strobe period ("when the chip enable (EMA_CS[n]) is asserted ")?

So how could I have obtained the correct functional and timing characteristics of the EMIFA data bus within the Asynchronous Read Cycle?

BR,
   Denis