AM37xx: Software Booting Configuration (TRM chapter 26.4.4)

Hi all,

could you provide an update on this issue??

Thanks,

--Gunter

In reading the TRM it looks like the word at 0x48002910 is a pointer to that structure in memory.

0x48002910: 14 29 00 48

0x48002914: 01 AA 00 CF

etc.

Hi all,

still trying to find the right format

To summarize

Using TRM Table 13-75 for CONTROL_SAVE_RESTORE_MEM

Wake-Up Booting by ROM Code

In CORE OFF power state, all configurations outside the WKUP power domain are reset and must be

restored to restart the system in the condition it was in before being stopped. After an MPU and CORE

power domain wake-up reset, the ROM code restores the SDRC and clock settings to allow a jump to a

public restore function. This public restore function is specifically implemented by users to restore their

own hardware and software environments. Users must set the public restore function address in the public

restore pointer field of the CONTROL_SAVE_RESTORE_MEM structure.

The CONTROL_SAVE_RESTORE_MEM memory of the SCM saves and restores mandatory information

to automatically reconfigure the SDRC and PRCM registers. The SDRC and clock registers must be

saved by users in the respective structures (see Table 26-50 and Table 26-51) in the SCM (scratchpad

memory) before going to off mode to be automatically restored on wake-up boot by the ROM code.

The size of CONTROL_SAVE_RESTORE_MEM is 240 bytes starting at the hardware physical address

0x48002910 to 0x480029FF. Figure 26-31 shows the memory format that must be obeyed to handle the

context restoration.

Using Figure 26-31 CONTROL_SAVE_RESTORE_MEM Format

Using Tables 26-50 and 51

Here is my thought:

0x48002910  Pointer to Boot Config structure

0x48002914 … 0x480029C0 PRCM registers save, SDRC registers save – Let’s not touch this area!

0x480029C0 … 0x480029FF Area for Actual booting configuration structure

So I am thinking to put the boot config structure in as follows:

0x48002910   C0 29 00 48

0x480029C0   01 AA 00 CF

(use what you had before)

…

Do you agree with this?

Now I need to look at the right boot config structure itself.

Thanks,

--Gunter

Hi all,

With the above in mind, our first test will be

0x48002910         C0 29 00 48          pointer to boot config

Boot config

0x480029C0        01 AA 00 CF         sync key for section 1

0x480029C4        0C 00 00 00          size of section 1

0x480029C8        1E 00 06 00          disable all CH, first boot device MMC1

0x480029CC        05 00 06 00          second boot device MMC2, third boot device MMC1

0x480029E0         05 00 00 00          fourth boot device MMC2, 2 bytes of padding

No further sections

This is using TRM Table 26-12.

Please comment if anyone has tried this.

Thanks,

--Gunter

Gunter,

Have you tried setting all of them to MMC1(given below) or UART boot? This will give a clear idea whether its really picking your custom settings or not. 

0x480029C0        01 AA 00 CF

0x480029C4        0C 00 00 00

0x480029C8        1E 00 06 00          

0x480029CC        06 00 06 00          

0x480029E0         06 00 00 00

How are you writing and reading the scratch pad memory?

Hi Renjith,

we have sucessfully used the following scratchpad memory for software boot configuration. This worked:

0x48002910         C0 29 00 48          pointer to boot config

Boot config

0x480029C0        01 AA 00 CF         sync key for section 1

0x480029C4        0C 00 00 00          size of section 1

0x480029C8        1E 00 06 00          disable all CH, first boot device MMC1

0x480029CC        05 00 06 00          second boot device MMC2, third boot device MMC1

0x480029E0         05 00 00 00          fourth boot device MMC2, 2 bytes of padding

We are assuming the memory allocations from the TRM and have tried not to overwrite anything.

Regards,

--Gunter