Two different devices on EMIF lines

Vijay,

The issue is that you've set the NAND timings to old value even if the clock has changed. So, you've to change the timing values in the EMIF controller registers according to the new clock. 

Btw, what exactly is the throughput issue? What is the current throughput and expected throughput?

Renjith,

Even we tried to change CE3CFG registers for tuning timing parameters as per NAND device.

NAND Flash is not detecting if EMIF freq is 91.20 MHz, Due to this,if we reduce freq from 91.20 MHz to 41 MHz, our throughput will be reducing between OMAPL138 to FPGA.

Vijay,

I need more time to figure the exact issue. But meanwhile, what is the throughput requirements that you have? There are better ways to achieve better throughput, than just by increasing the clock.

Renjith,

For 91.20MHz, I am getting  approximately 100Mb/S. I need to check on 41MHz

Vijay,

How are you doing the read? Are you using DMA for the same or are you reading using ARM? Is the current 12MB/sec is the required throughput?

Also for NAND have yo tried the maximum timings and saw?

Renjith,

Currently we are using ARM. Yes required throughput is around 12MB/s.

We have tried timing parameters as per device timing parameters (Micron -MT29F8G08ABABAWP-IT) & also using maximum 0x3FFFFFFC, we have tried, i am facing same issue No Nand device found with 91.20 Mhz

Vijay,

I need some time to checkout the frequency part. But you can try to optimize your FPGA read routine. If you can share the portion of code, I can have a look at it. You can email me if you don't prefer posting here.