How to slow down DDR frequency

Hi,

Which software release are you using for this? Is it Android or Ubuntu or any other customer OS?

Regards, Satheesh

HI Satheesh

we use android ICS software.

thanks

Hi Sam,

I see that you have already posted a similar question earlier and this has been answered. See the link below:

http://e2e.ti.com/support/omap/f/849/t/189028.aspx

Is there anything additional you would like to know on top of this? As mentioned in the above mentioned post, the PM framework controls the DDR frequency once the kernel comes up. It is not recommended to override this unless you have a very compelling reason.

Regards, Satheesh

HI Satheesh

some of our board have error about "SGX recovery trigger".BUT other board not have this issue.

all of those board are design same hardware schematic and same component.

So we try to slow down DDR frequency to clarify the issue is ddr or not.

thanks.

Sam,

The DDR frequency is set in the x-loader in /cpu/omap4/sdram_elpida.c through the .config_init, .config_final, and .mr2 values.  Typically the .config_init sets the DDR frequency to a lower value, such as 200MHz, and the .config_final sets the DDR frequency to a higher value, such as 400MHz, after the rest of the DDR configuration has been set.  This is done through the Read Latency field of SDRAM_CONFIG, which must match the MR2 register.

You could confirm with omapconf that the DDR frequency is set as expected after the kernel loads:

http://e2e.ti.com/support/omap/f/849/p/216016/762013.aspx#762013

Perhaps you could post details about the SGX recovery trigger error (as a separate E2E thread) in case our graphics experts have any other suggestions on this.

Regards,
Gina 

Hi Gina,

I have post SGX recovery issue to new thread.

i got CDDS mail that new document  naming "LPDDR2 Configuration on OMAP44xx" for ddr setting.

this new documentt mention "mtest" command can use for memory test.

but when we execute "mtest 0x80000000 0x80000010"

system run memory test long time. 

Can you help to explain how to set parameter for mtest command and each parameter mean. 

mtest [start [end [pattern [iterations]]]]

thanks

Sam,

The mtest will run indefinitely until either there is an error, or you hit Ctrl+C to stop it.  If your mtest ran for a long time with no failure, then likely the region of DDR from 0x80000000 to 0x80000010 has no issues.  You can use the mtest command:

mtest [start [end [pattern [iterations]]]]

if you want to specify the particular pattern to read/write to the memory and the number of iterations to run for.  However, normally this is not necessary, and you can instead just use the mtest command:

mtest start end

which runs the mtest over the region of DDR from 'start' to 'end'.

Regards,
Gina 

Hi Gina ,

thank for you explain mtest.

mtest run on our failure board still fine.

we want to speed down ddr frequency to 200M and want ddr run in 200M all time.

can you give us some advice how to modify.

thanks.

sam

Hello Sam,

Note that as MPU/IVA traffic increases, the sw releases have the lpddr ramp up to the 400MHz frequency to deal with the increased memory activity.  If you always keep the lpddr at the lower frequency then the lpddr may not be able to keep up with higher traffic.

To limit the lpddr freq to 200MHz, you can try modifying omap4_core_dpll_m2_set_rate() in arch/arm/mach-omap2-dpll44xx.c.  Setting the rate variable to 400000000 should keep the lpddr at 200MHz (the dpll gets divided by 2 before feeding into the lpddr clock).  You can check the LPDDR frequency with omapconf 1.50

Regards,

Alex

Hi Alex,

Unlucky, system will die if we set rate to 400000000(set to 933333333 system also hang).

we add log in omap4_core_dpll_m2_set_rate(),log show kernel booting system will shwitch M2 clock between 933333333 and 466666666 several time.

It's seem  we can not hard code "rate" value in omap4_core_dpll_m2_set_rate().

Any further opinion is grateful

Sam,

Have you tried setting rate = 466666666?  Also, just to make sure did add that line right after the    unsigned long flags;   ?

I tried a 4470 with the above change and the LPDDR shows 233MHz statically on omapconf.  The system gets stuck at kernel bootup.

However I must again state that keeping the LPDDR at a low frequency is not recommended as it cannot keep up with higher MPU/IVA traffic, so it's not surprising if the system runs into issues.

Regards,

Alex

HI ALex ,

Thank for you advice. we try to set rate as 466666666,android file system can boot success.

we try to install omapconf to confirm ddr clock but always fail.

we raise another issue for omapconf install

http://e2e.ti.com/support/omap/f/849/t/221707.aspx

if any result we will post here .

thanks

sam 

Hi alex

we can use omapconf to dump emif register now.

How to confirm ddr is running in 233M frequency(USE which register to calculate).

Please advices

thanks