This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

[ICE demoboard] AM3359 SPI1

Hi.

I'm trying to configure SPI1 as SPI master, pin mux mode 3 (sclk routed to MCASP0_ACLKX, SPI1_D0 and SPI1_D1 to MCASP_FSX and MCASP0_AXR0) to load configuration data to an  Altera CycloneIII fpga.

The configuration code and the transmission routine seems to work fine, but I can't see any clock activity out of pin MCASP0_ACLKX: after configuration the oscilloscope probe shows that pin toggles from tri-state to output driving to ground. 

Setting SPICLK=1 in MCSPI_SYST doesn't drive high CLKSPI output pin:

"If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the CLKSPI line is driven high or low according to the value written into this register.", as stated in echnical reference manual page 4490.

This is configuration code (cut&paste from examples in sdk1.0.04):

...

...

// |
// | SPI1 peripheral SETUP
// |
MUX_VAL(CONTROL_PADCONF_MCASP0_ACLKX, (IDIS | IEN | MODE3 ));
MUX_VAL(CONTROL_PADCONF_MCASP0_FSX, (IDIS | PD | MODE3 ));
MUX_VAL(CONTROL_PADCONF_MCASP0_AXR0, (IEN | (1<<4) | MODE3 ));

spi1Init();

...

void spi1Init(void)
{
unsigned int retVal = 0;

/* Setup SPI peripheral */
/* Enable the clocks for McSPI1 module.*/
McSPI1ModuleClkConfig();
/* Reset the McSPI instance.*/
McSPIReset(SOC_SPI_1_REGS);
/* Enable chip select pin.*/
McSPICSDisable(SOC_SPI_1_REGS);
/* Enable master mode of operation.*/
McSPIMasterModeEnable(SOC_SPI_1_REGS);
McSPIChannelEnable(SOC_SPI_1_REGS, MCSPI_CHANNEL_0);
/* Perform the necessary configuration for master mode.
** If combination of trm and IS,DPE0 and DPE1 is not valid then retVal is
** false.
*/
retVal = McSPIMasterModeConfig(SOC_SPI_1_REGS, MCSPI_SINGLE_CH,
MCSPI_TX_ONLY_MODE, MCSPI_DATA_LINE_COMM_MODE_6,
MCSPI_CHANNEL_0);

/*
** If combination of trm and IS,DPE0 and DPE1 is not valid then retVal is
** false.
*/
if(!retVal)
{
return;
}
/*
** Default granularity is used. Also as per my understanding clock mode
** 0 is proper.
*/
McSPIClkConfig(SOC_SPI_1_REGS, MCSPI_IN_CLK, MCSPI_OUT_FREQ/16, MCSPI_CHANNEL_0,
MCSPI_CLK_MODE_0);
/* Configure the word length.*/
McSPIWordLengthSet(SOC_SPI_1_REGS, MCSPI_WORD_LENGTH(8), MCSPI_CHANNEL_0);

/* Set polarity of SPIEN to low.*/
McSPICSPolarityConfig(SOC_SPI_1_REGS, MCSPI_CS_POL_LOW, MCSPI_CHANNEL_0);

}

This is the code used to send data out to the spi master:

static void McSPITransfer (unsigned char *p_tx, unsigned int len)
{

while(len)

{

while(MCSPI_INT_TX_EMPTY(MCSPI_CHANNEL_0) !=
(McSPIIntStatusGet(SOC_SPI_1_REGS) & MCSPI_INT_TX_EMPTY(MCSPI_CHANNEL_0)));
McSPITransmitData(SOC_SPI_1_REGS, *p_tx, MCSPI_CHANNEL_0);

p_tx++;
len--;

}
}

  • Hi Eugenio,
     
    What board are you using? Is it a custom board?
     
    Best Regards
    Biser
  • The board is ICE board rev 1.0A.

    I've tried CLK_MODE_6:

    McSPIClkConfig(SOC_SPI_1_REGS, MCSPI_IN_CLK, MCSPI_OUT_FREQ/16, MCSPI_CHANNEL_0,MCSPI_CLK_MODE_6);

    and the signal goes high (and stays high), so there is no concern in pin output driver or signal contention.


    I'm sorry for this trivial issue, but it's blocking the developement of a custom board with an fpga that must be configured by cpu through SPI1...

  • Hi Eugenio,
     
    Processor pin MCASP0_FSX (ball B13) is not connected on the ICE EVM. And SPI1 on this pimux is connected to an expander chip U25. Why don't you try SPI0 with SPI0_CS1, which come out on the expander connector J12?
     
    Best Regards
    Biser
  • In our custom board SPI1 will be used, and I'm developing the bootloader code needed to start pre-production tests.In the meanwhile I'm testing this code on ICE eval board.

    I'm conscious about ball B13 not being connected, but I'm just looking at SCLK coming out from master SPI1 to U25 spi clock input in demoboard with an oscilloscope.

    I think I'm missing something somewere in SPI1 init procedure:

    - pinmux should be ok: I can see SCLK low or high when master is idle, depending on clock mode configuration;

    - transmit code (cut&paste from starterware examples) seems to send data, but...

    - ... there is no activity on SCLK pin.

    I've read TRM spi section over and over, but everything seems ok to me.

  • I understand Eugenio. I will try to pull in some more help on this.
     
    Best Regards
    Biser
  • It was related to some preprocessor's defines.

    Setting project's defines this way corrects the problem: