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Pad Control Register, PULLUDEN

Dear TI Support Team

In the AM335x Technical Reference Manual, spruh73f, section 9.2.2, the Bit PULLUDEN is described as follows:

0   Pullup/pulldown disabled
1   Pullup/pulldown enabled

However, the code generated from the pin mux utility suggests the contrary:

#define PD (0 << 3)
#define PU (2 << 3)
#define OFF (1 << 3)

And so does the code in the TI PSP kernel and u-boot pin mux files.

Is the Technical Reference Manual wrong here?

Thank you and best regards,

Matthias