Hi all,
I have a question regarding the behaviour of the built-in FIFO of the McSPI module within DM8148 device.
I want to run the McSPI module in slave mode, transmit-and-receive mode enabled with FIFO support and interrupt control.
Reception with the FIFO and interrupts works fine, but in transmit direction I'm missing the TX_empty events.
What my software does: It enables the SPI channel, then handles the automatically raised TX_empty event. Within interrupt service routine the FIFO gets filled up to maximum level for the first time. Some time later the SPI master starts the transmission and I would expect that my SPI slave gets subsequent TX_empty events, after McSPI_XFERLEVEL[AEL]+1 bytes have been sent out, so that my interrupt service routine can refill the FIFO with (AEL + 1) bytes. But these subsequent TX_empty events I am currently missing. Any hints why this happens?
Thanks in advance and best regards
Andre
