C67x+ Instruction Set Documentation Error

Julxhino Gocllari

Other Parts Discussed in Thread: TMS320C6720

This is a warning for anyone building their own assembler, like myself. I've noticed that the documentation (Literature Number: SPRU733A) is incorrect in a few places. I've been having issues with the AND instruction. It executes fine on the .L1 or .L2 units, but however when I try to execute it on the .S1 or .S2 units, it won't work. I've checked the opcode over and over and over again, hoping that I was stupid and the documentation was correct, but that's not the case. I made sure that there wasn't any functional unit constraints or delay slot issues. I didn't even run any instructions in parallel, everything was sequential. I'm not sure what's going on here, I don't think I'm losing my mind, but who knows. Anyhow if anyone has any tips/comments/corrections/anything, please let me know!

over 12 years ago

0 RandyP over 12 years ago

TI__Guru* 84110 points

Julxhino,

Sorry you are having trouble with this.

The best tip is: do not try to write your own assembler. We already did it, and our assembler works pretty well, thank you very much.

As a comment: you will have to supply more information to get anyone to be able to make any specific comments. But honestly, we do not support a lot of assembly coding and we are not likely to have people who can help you with writing your own assembler.

This is a software tools issue, so this post will get moved to the TI Compiler Forum where also assembler questions are discussed.

I tried a simple test with

void main(void)
{
asm(" AND .s1 a1,a2,a3");
asm(" AND .s2 b1,b2,b3");
asm(" AND .l1 a1,a2,a3");
asm(" AND .l2 b1,b2,b3");
}

It ran fine on the C6713 simulator, although that is not a final say. I do not have a board to try it on, and this is as far as I am going to go with it.

My opinion is that you have made a mistake, but I do not know which device you are running this on or which simulator you are running it on or exactly what code / machine code. So it looks like the TI assembler generates working code but yours does not. So I recommend you do some more digging or give us more detail.

Regards,
RandyP

0 Julxhino Gocllari over 12 years ago in reply to RandyP

Prodigy 105 points

Randy,

Thank you very much for replying. I know I wasn't very specific about my issue, probably because I wasn't sure if any one was going to reply or not, but seeing how you replied and are willing to at least try to help me out, I'll give you some more details.

1) First of all, I'm experimenting with the TMS320C6720.

2) I'm booting in parallel flash mode, which means that the first 1024 bytes inside my SST39LF040, parallel flash(8-bit flash), get loaded into the internal RAM of the DSP and execution begins at 0x1000 0004.

3) My custom built assembler generates the 1s and 0s that go unto the flash.

4) I've tested my assembler/linker and it works fine, I had the TMS320C6720 communicating with a PIC18F4550 via I2C, where the TI was a slave and the PIC was the master, this was how I was debugging and verifying my results.

5) I'm almost 100% sure that one or more of the bits in the opcode for the .S1 or .S2 listed on page 126 of document: SPRU733A, is probably incorrect. The .L1 or .L2 versions of the AND instruction work fine.

6) On another note you ran your sample code for a C6713 simulator, I'm running code on the C6720 chip itself (HARDWARE!!!), its a little different. Also the C6720 and the C6713 have slightly different internal architectures. I did also notice that some of the text inside C67x/C67x+ is misleading and somewhat confusing, especially the description for the CSR(Control Status Register), page 39 of the SPRU733A. The C6720 does not have the data/program cache split up, like the C6713, but yet the description of the CSR lists both the program cache and the data cache. It's like I don't know what to believe, the data sheet of the TMS320C6720 or the C67/C67x+ instruction set.

I'm not the kind of person that runs to a forum for an answer as soon as I encounter a problem. I've done a lot of reading and testing, I wouldn't be telling you all this unless I really thought that there were errors on the SPRU733A.

0 Jakez over 12 years ago in reply to Julxhino Gocllari

Expert 1950 points

Hello,

If the problem is not solved yet, you can find below instruction words generated by TI tools for some AND instructions (same for targets C67 & C67+). It's up to you to check the documentation coherency.

01040F78                AND    .L1   A0,A1,A2
01040F7A                AND    .L2   B0,B1,B2
01041F78                AND    .L1x A0,B1,A2
01003F7A                AND    .L2x A0,B1,B2
010407E0                AND    .S1   A0,A1,A2
010407E2                AND    .S2   B0,B1,B2
010417E0                AND    .S1x A0,B1,A2
010037E2                AND    .S2x A0,B1,B2
010427A0                AND    .S1   1,A1,A2
01042F58                AND    .L1   1,A1,A2
410427A0           [B1] AND    .S1   1,A1,A2
41042F58           [B1] AND    .L1   1,A1,A2

Good luck,

Jakez

PS: If necessary, post any other suspicious instruction(s); I can post back the "officially" generated instruction codes, if it helps.

Edit: This post is an answer to Julxino only, of course.

0 RandyP over 12 years ago in reply to Jakez

TI__Guru* 84110 points

Julxhino,

Julxhino said:
4) I've tested my assembler/linker and it works fine,
5) I'm almost 100% sure that one or more of the bits in the opcode for the .S1 or .S2 listed on page 126 of document: SPRU733A, is probably incorrect. The .L1 or .L2 versions of the AND instruction work fine.

This is not enough information. "one or more of the bits" and "the documentation is incorrect in a few places" (original post) do not tell us where to look. You have spent a lot of time on this, so please be specific about which bits you think are wrong and where the "few places" are. We will be eager to correct any errors, but all we have to go on right now is that your custom assembler does not work because of some error in our documentation. Please help us with specifics.

What machine code 1's and 0's do you generate for the AND instruction list that Jakez lists above?

One thing I noticed comparing Jakez's list to the documentation is that for the .S unit instructions, the opcodes above have bit4=0 while the SPRU733A has bit4=1.

Now that this thread was finally moved to the Compiler Forum, the right people will be able to address this question. Best of luck, and if you are correct as it appears you are then thank you for bringing this to our attention. If there are other discrepancies, please tell us what those are.

Regards,
RandyP

0 Archaeologist over 12 years ago in reply to RandyP

TI__Guru* 84285 points

This is almost certainly not a compiler issue.

If the TI-assembler-generated AND.S instructions work on the hardware, then the assembler must be correct (as far as the existing hardware is concerned). Given that the assembler and hardware agree, the CPU documentation is the odd man out. This should be considered a CPU documentation bug until proven otherwise. The compiler team does not write the CPU documentation.

0 RandyP over 12 years ago in reply to Archaeologist

TI__Guru* 84110 points

Okay, we are back in the C67x Single Core DSP Forum and will look at this as a documentation issue.

Julxhino,

You have stated that there are multiple errors in the documentation. Please itemize those so they can all be examined.

Regards,
RandyP

0 Julxhino Gocllari over 12 years ago in reply to RandyP

Prodigy 105 points

I would like to thank all of you for your time and effort, especially Jakez, thank you so much for printing out the opcodes for those various AND instructions. It appears as if we've found where the error is: On Page 3-66 of the document: SPRU733A, (pdf page 126), bit 4 of the .S unit opcode should be a '0', not a '1'. Its funny how one bit makes all the difference =)

Once again thank you all, especially Jakez and Randy

Julxhino

Processors

Processors forum

C67x+ Instruction Set Documentation Error