How to configure DSI when use dsi1 and dsi2 linked simultaneously to a single panel ?

Hi,

Could you provide some information on the panel you are using for this? There are numerous changes required in software for enabling this feature and this is not part of the default release. Also have you identified the bridge chip you are planning to use for this?

Thanks, Satheesh

HI,

The Panel we use is a 2048x1536 lcd with EDP interface. so we use a DSI-2-EDP chip which use 8 data lanes and 2 clock lanes for input  between omap4470 and the panel.  

Any suggestions on how to lighting this panel? If any branch or codes we can reference ?

Regards

Here is what I think needs to be done:

• The framebuffer is divided in two.
• Each half is sent to an overlay, say VID1 and VID2
• Connect VID1 to LCD1 and VID2 to LCD2
• For DSI Clocks we should use independent PLLs using same reference clock (sys_clock) and configured for same PLL frequency
• The bridge should be able to buffer the DSI data to allow delay between packets from DSI1 and DSI2

Maybe in order to start working on this, you could try u-boot, instead of the kernel, that way you can have the required sequence to bring it up faster, without all the kernel hassle.

There is a u-boot splash application for Blaze Tablet here:

http://review.omapzoom.org/#/c/23975/

It initializes DISPC, DSI1 and a GFX Overlay. Maybe you can change it to use both DSI1 and DSI2 and use VID1 and VID2 overlays.

Then change the bridge configuration code to your bridge.

Regards

Rafael Rodriguez

Hi

Thanks for your reply.  I have below questions to makes it work:

Is there a resolution limit for overlays on OMAP4470 ? If the limit is smaller than 2048x1536, it means i need to split the  surface into 2 parts, and each one sent to different overlay? Now how to split the surface ? Is there some hardware feature to do this ?

Regards

Dear

Could anyone give me some advise?

Regards

Hi Stanley

Sorry for the delay. I was gathering info on Large Screen Dual DSI.

The limit with the overlays is not related to the size, but to the bandwidth. The hardware-level BW for those ports on OMAP4 is not balanced naturally between the two ports.

For DSI1 we have a limit of  824 Mbps per lane, that is 824Mbps*4 lanes=3296 Mbps

For DSI2 we have the limit of 900 Mbps per lane, that is 900Mbps*2 lanes=1800 Mbps

So you need to split the framebuffer, no in half, but 2/3 to DS1 and 1/3 to DSI2.

How to split the framebuffer?

The 2048x1536 framebuffer is a single chunk of DDR memory.

You can use DISPC_VID1_BAj to point to the beginning of th framebuffer and DISPC_VID2_BAj to point to 2/3 of the total size.

Also you have to use the registers DISPC_VID1_SIZE and DISPC_VID2_SIZE to define the proper size.

And then on the register DISPC_VID1_ATTRIBUTES[30:31] you can send the output to the LCD1 and then to DSI1

and the same for DISPC_VID2_ATTRIBUTES[30:31].

Sadly, this is only a rough idea of what you can try.

There seems to be no one on TI yet on OMAP4 with a 2048x1536 LCD panel, so there is no one to refer to who has actually supported this on OMAP4.

The current work has been focused for OMAP5 for a Texas Instruments Dual DSI bridge, not toshiba.

regards

Rafael

Hi Rafael

Yes we use TC358770 from toshiba as the dsi-2-edp with 2 dsi inputs. As you mentiond, the OMAP5 default release will contains Dual DSI bridge support ? And  the DSI bridge  is a single chip from TI  or be integrated into OMAP5 SOC ?
We works on 4470 and TC358770 is only for pre-research, our product will use OMAP5 platform. So could you please provide more infos on this.

Regards 

Hi Stanley

Thanks for your patience. I am trying to gather info on the OMAP5 qxga and higher resolution solutions and if possible a roadmap or some release dates.

I will be back to you soon

Regards

Rafael