AM387x UART3 problem?

Michi Yama

Other Parts Discussed in Thread: AM3874

Hi,

Our customer is developing AM3874 system.

Customer board uses UART3 as output port for deubg information.

But they have a trouble now. UART3 communication does not work correctly. As you know, TI's EVM uses UART0 as debug port. Customer firmware works well with TI's EVM(UART0). But their firmware does not work with customer's board(UART3).

According to customer's analysis, data is ok. But it seems that the stop bit is longer than other bits ( start bit, data bit ). Under 115.2kbps condition, the pulse width is 8.68us with TI EVM. But its pulse width is 9.24us with customer board.

I attached UART peripheral register's memory dump list. Please see the file.

Fullscreen 7506.UART_REGISTER compare.txt Download

��EVM
UART0 Peripheral Registers
R;0x48020000|000000eb 00000000 000000c1 00000003 
R;0x48020010|00000003 00000060 00000000 00000000 
R;0x48020020|00000000 00000000 00000000 00000000 
R;0x48020030|00000044 00000006 00000040 00000000 
R;0x48020040|00000000 00000004 00000000 00000000 
R;0x48020050|50411e03 00000000 00000001 000000ff 
R;0x48020060|00000069 00000000 00000000 00000000 
R;0x48020070|00000003 0000001a 00000000 00000000 

R;0x48020000|0000001a 00000000 00000000 000000bf Divisor latch enable. Allows access to DLL and DLH.
R;0x48020010|00000000 00000000 00000000 00000000 
R;0x48020020|00000000 00000000 00000000 00000000 
R;0x48020030|00000044 00000006 00000000 00000000 
R;0x48020040|00000000 00000004 00000000 00000000 
R;0x48020050|50411e03 00000000 00000001 000000ff 
R;0x48020060|00000069 00000000 00000000 00000000 

PRCM Peripheral Registers(CM_DPLL)
R;0x48180300|00000000 00000000 00000000 00000000 
R;0x48180310|00000000 00000000 00000000 00000000 
R;0x48180320|00000000 00000003 00000000 00000000 24h 0x3 = SYSCLK10_DIV_4
R;0x48180330|00000007 00000007 00000003 00000000 
R;0x48180340|00000002 00000003 00000007 00000000 
R;0x48180350|00000000 00000000 00000000 00000000 
R;0x48180360|00000000 00000000 00000000 00000000 
R;0x48180370|00000000 00000000 00000000 00000000 
R;0x48180380|00000000 00000000 00000000 00000000 
R;0x48180390|00000001 00000001 00000001 00000001 
R;0x481803a0|00000001 00000001 00000001 00000002 
R;0x481803b0|00000000 00000000 00000000 00000000 
R;0x481803c0|00000000 00000000 00000000 00000000 
R;0x481803d0|00000000 00000000 00000000 00000000 
R;0x481803e0|00000000 00000000 00000000 00000000 
R;0x481803f0|00000000 00000000 00000000 00000000 

PLLSS Peripheral Registers
R;0x481c5000|4e8c0001 00000000 00000000 00000000 
R;0x481c5010|0000002a 00000000 00000000 00000000 
R;0x481c5020|00000000 00000000 00000000 00000000 
R;0x481c5030|00000000 00000000 00000000 00000000 
R;0x481c5040|1eda4c3d 00000000 00000000 0c11e819 
R;0x481c5050|00000000 00000000 00010001 0000003c 
R;0x481c5060|00000000 00000000 00000000 00000630 
R;0x481c5070|00000001 00000000 00000000 00000000 
R;0x481c5080|00000030 08110811 00000000 00000000 
R;0x481c5090|00010013 000001f4 08000000 00000000 
R;0x481c50a0|00000000 c0000630 00000000 00000000 
R;0x481c50b0|00000030 08110811 00000000 00000000 
R;0x481c50c0|00040013 00000320 08000000 00000000 
R;0x481c50d0|00000000 c0000630 00000000 00000000 
R;0x481c50e0|00000030 08110811 00000000 00000000 
R;0x481c50f0|00020013 00000264 08000000 00000000 
R;0x481c5100|00000000 c0000630 00000000 00000000 
R;0x481c5110|00000030 09110813 00000000 00000000 
R;0x481c5120|00040013 00000320 04000000 00000000 
R;0x481c5130|00000000 c0000630 00000000 00000000 
R;0x481c5140|00000030 08110811 00000000 00000000 
R;0x481c5150|00020013 00000320 08000000 00000000 
R;0x481c5160|00000000 c0000630 00000000 00000000 
R;0x481c5170|00000030 09110813 00000000 00000000 
R;0x481c5180|00040013 00000320 08000000 00000000 
R;0x481c5190|00000000 c0000638 00000000 00000000 
R;0x481c51a0|00000030 09110813 00000000 00000000 
R;0x481c51b0|000a0013 0000021c 04000000 00000000 
R;0x481c51c0|00000000 c0000630 00000000 00000000 
R;0x481c51d0|00000030 08110811 00000000 00000000 
R;0x481c51e0|00110013 000001fe 08000000 00000000 
R;0x481c51f0|00000000 c0000630 00000000 00000000 
R;0x481c5200|00000030 09910812 00000000 00000000 
R;0x481c5210|00050013 00000174 08000000 00000000 
R;0x481c5220|00000000 e0000161 00000000 00000000 
R;0x481c5230|00000030 08110811 00000000 00000000 
R;0x481c5240|00020013 000001f4 08000000 00000000 
R;0x481c5250|00000000 c0000630 00000000 00000000 
R;0x481c5260|00000030 281b0811 00000000 00000000 USB
R;0x481c5270|00050013 000003c0 04000000 00000000 
R;0x481c5280|00000000 c0000630 00000000 00000000 
R;0x481c5290|00000030 08110811 00000000 00000000 
R;0x481c52a0|00020013 00000320 04000000 00000000 
R;0x481c52b0|00000000 c0000630 00000000 00000000 
R;0x481c52c0|00000000 00000000 00000000 00000000 
R;0x481c52d0|00000000 00000000 00000000 00000000 
R;0x481c52e0|09240924 00000000 00000004 00000000 
R;0x481c52f0|00000000 00000000 00000000 00000000 

-------------------------------------------------------
��FANUC UART3
UART3 Peripheral Registers
R;0x481a6000|00000001 00000000 000000c1 00000003 
R;0x481a6010|00000003 00000060 00000020 00000000 
R;0x481a6020|00000000 00000000 00000000 00000000 
R;0x481a6030|00000064 0000000c 00000040 00000000 
R;0x481a6040|00000000 00000004 00000000 00000000 
R;0x481a6050|50411e03 00000008 00000001 000000ff SYSC IDLEMODE 1h No-idle: Idle request is never acknowledged.
R;0x481a6060|00000069 00000000 00000000 00000000 
R;0x481a6070|00000003 0000001a 00000000 00000000 

R;0x481a6000|0000001a 00000000 00000000 000000bf Divisor latch enable. Allows access to DLL and DLH.
R;0x481a6010|00000000 00000000 00000000 00000000 
R;0x481a6020|00000000 00000000 00000000 00000000 
R;0x481a6030|00000064 0000000c 00000000 00000000 
R;0x481a6040|00000000 00000004 00000000 00000000 
R;0x481a6050|50411e03 00000008 00000001 000000ff 
R;0x481a6060|00000069 00000000 00000000 00000000 
R;0x481a6070|00000003 0000001a 00000000 00000000 

PRCM Peripheral Registers(CM_DPLL)
R;0x48180300|00000000 00000000 00000000 00000000 
R;0x48180310|00000000 00000000 00000000 00000000 
R;0x48180320|00000000 00000003 00000000 00000000 24h 0x3 = SYSCLK10_DIV_4
R;0x48180330|00000007 00000007 00000003 00000000 
R;0x48180340|00000002 00000003 00000007 00000000 
R;0x48180350|00000000 00000000 00000000 00000000 
R;0x48180360|00000000 00000000 00000000 00000000 
R;0x48180370|00000000 00000000 00000000 00000000 
R;0x48180380|00000000 00000000 00000000 00000000 
R;0x48180390|00000001 00000001 00000001 00000001 
R;0x481803a0|00000001 00000001 00000001 00000002 
R;0x481803b0|00000000 00000000 00000000 00000000 
R;0x481803c0|00000000 00000000 00000000 00000000 
R;0x481803d0|00000000 00000000 00000000 00000000 
R;0x481803e0|00000000 00000000 00000000 00000000 
R;0x481803f0|00000000 00000000 00000000 00000000 

PLLSS Peripheral Registers
R;0x481c5000|4e8c0001 00000000 00000000 00000000 
R;0x481c5010|0000002a 00000000 00000000 00000000 
R;0x481c5020|00000000 00000000 00000000 00000000 
R;0x481c5030|00000000 00000000 00000000 00000000 
R;0x481c5040|1eda4c3d 00000000 00000000 0c11e819 
R;0x481c5050|00000000 00000000 00010001 0000003c 
R;0x481c5060|00000000 00000000 00000000 00000638 
R;0x481c5070|00000001 00000000 00000000 00000000 
R;0x481c5080|00000030 08110811 00000000 00000000 
R;0x481c5090|00010013 000001f4 08000000 00000000 
R;0x481c50a0|00000000 c0000638 00000000 00000000 
R;0x481c50b0|00000030 08110811 00000000 00000000 
R;0x481c50c0|00040013 00000320 08000000 00000000 
R;0x481c50d0|00000000 c0000638 00000000 00000000 
R;0x481c50e0|00000030 0711080f 00000000 00000000 
R;0x481c50f0|00020013 00000214 08000000 00000000 
R;0x481c5100|00000000 c0000638 00000000 00000000 
R;0x481c5110|00000030 08110811 00000000 00000000 
R;0x481c5120|00040013 00000320 04000000 00000000 
R;0x481c5130|00000000 c0000638 00000000 00000000 
R;0x481c5140|00000030 08110811 00000000 00000000 
R;0x481c5150|00020013 00000320 08000000 00000000 
R;0x481c5160|00000000 c0000638 00000000 00000000 
R;0x481c5170|00000030 08110811 00000000 00000000 
R;0x481c5180|00040013 00000320 08000000 00000000 
R;0x481c5190|00000000 c0000638 00000000 00000000 
R;0x481c51a0|00000030 08110811 00000000 00000000 
R;0x481c51b0|000a0013 0000021c 04000000 00000000 
R;0x481c51c0|00000000 c0000638 00000000 00000000 
R;0x481c51d0|00000030 08110811 00000000 00000000 
R;0x481c51e0|00080013 00000252 08000000 00000000 
R;0x481c51f0|00000000 c0000638 00000000 00000000 
R;0x481c5200|00000030 08910810 00000000 00000000 
R;0x481c5210|00050013 00000174 08000000 00000000 
R;0x481c5220|00000000 e0000161 00000000 00000000 
R;0x481c5230|00000030 08110811 00000000 00000000 
R;0x481c5240|00020013 000001f4 08000000 00000000 
R;0x481c5250|00000000 c0000638 00000000 00000000 
R;0x481c5260|00000030 281b0811 00000000 00000000 
R;0x481c5270|00050013 000003c0 04000000 00000000 
R;0x481c5280|00000000 c0000638 00000000 00000000 
R;0x481c5290|00000030 0711080f 00000000 00000000 
R;0x481c52a0|00020013 00000320 04000000 00000000 
R;0x481c52b0|00000000 c0000638 00000000 00000000 
R;0x481c52c0|00000000 00000000 00000000 00000000 
R;0x481c52d0|00000000 00000000 000000a8 00000000 
R;0x481c52e0|09240924 00000000 00000000 00000000 
R;0x481c52f0|00000000 00000000 00000000 00000000 

PRCM Peripheral Registers CM_ALWON
R;0x48181500|00000000 00000000 00000000 00000000 
R;0x48181510|00000000 00000000 00000000 00000000 
R;0x48181520|00000000 00000000 00000000 00000000 
R;0x48181530|00000000 00000000 00000000 00000000 
R;0x48181540|00030000 00030000 00030000 00030000 
R;0x48181550|00000002 00000002 00000002 00030100 UART0,1,2
R;0x48181560|00030100 00000002 00030000 00000002 
R;0x48181570|00030000 00030000 00030000 00030000 
R;0x48181580|00000002 00030000 00000002 00000002 UART3,4,5
R;0x48181590|00000002 00030000 00030000 00030000 
R;0x481815a0|00070000 00000000 00030000 00000000 
R;0x481815b0|00030000 00000002 00030000 00030000 
R;0x481815c0|00030000 00000002 00000002 00000000 
R;0x481815d0|00000002 00000002 00040002 00000002 
R;0x481815e0|12500302 00000002 00000002 00000002 
R;0x481815f0|00000002 00030000 00030000 00030000 
-------------------------------------------------------
��FANUC UART0
UART0 Peripheral Registers
R;0x48020000|00000034 00000000 000000c1 00000003 
R;0x48020010|00000003 00000060 00000000 00000000 
R;0x48020020|00000000 00000000 00000000 00000000 
R;0x48020030|000000ff 0000000f 00000040 00000000 
R;0x48020040|00000000 00000004 00000000 00000000 
R;0x48020050|50411e03 00000008 00000001 000000ff SYSC IDLEMODE 1h No-idle: Idle request is never acknowledged.
R;0x48020060|00000069 00000000 00000000 00000000 
R;0x48020070|00000003 0000001a 00000000 00000000 

R;0x48020000|0000001a 00000000 00000000 000000bf Divisor latch enable. Allows access to DLL and DLH.
R;0x48020010|00000000 00000000 00000000 00000000 
R;0x48020020|00000000 00000000 00000000 00000000 
R;0x48020030|000000ff 0000000f 00000000 00000000 
R;0x48020040|00000000 00000004 00000000 00000000 
R;0x48020050|50411e03 00000008 00000001 000000ff 
R;0x48020060|00000069 00000000 00000000 00000000 
R;0x48020070|00000003 0000001a 00000000 00000000 

PRCM Peripheral Registers(CM_DPLL)
R;0x48180300|00000000 00000000 00000000 00000000 
R;0x48180310|00000000 00000000 00000000 00000000 
R;0x48180320|00000000 00000003 00000000 00000000 24h 0x3 = SYSCLK10_DIV_4
R;0x48180330|00000007 00000007 00000003 00000000 
R;0x48180340|00000002 00000003 00000007 00000000 
R;0x48180350|00000000 00000000 00000000 00000000 
R;0x48180360|00000000 00000000 00000000 00000000 
R;0x48180370|00000000 00000000 00000000 00000000 
R;0x48180380|00000000 00000000 00000000 00000000 
R;0x48180390|00000001 00000001 00000001 00000001 
R;0x481803a0|00000001 00000001 00000001 00000002 
R;0x481803b0|00000000 00000000 00000000 00000000 
R;0x481803c0|00000000 00000000 00000000 00000000 
R;0x481803d0|00000000 00000000 00000000 00000000 
R;0x481803e0|00000000 00000000 00000000 00000000 
R;0x481803f0|00000000 00000000 00000000 00000000 

PLLSS Peripheral Registers
R;0x481c5000|4e8c0001 00000000 00000000 00000000 
R;0x481c5010|0000002a 00000000 00000000 00000000 
R;0x481c5020|00000000 00000000 00000000 00000000 
R;0x481c5030|00000000 00000000 00000000 00000000 
R;0x481c5040|1eda4c3d 00000000 00000000 0c11e819 
R;0x481c5050|00000000 00000000 00010001 0000003c 
R;0x481c5060|00000000 00000000 00000000 00000630 
R;0x481c5070|00000001 00000000 00000000 00000000 
R;0x481c5080|00000030 09110813 00000000 00000000 
R;0x481c5090|00010013 000001f4 08000000 00000000 
R;0x481c50a0|00000000 c0000638 00000000 00000000 
R;0x481c50b0|00000030 08110811 00000000 00000000 
R;0x481c50c0|00040013 00000320 08000000 00000000 
R;0x481c50d0|00000000 c0000638 00000000 00000000 
R;0x481c50e0|00000030 09110813 00000000 00000000 
R;0x481c50f0|00020013 00000214 08000000 00000000 
R;0x481c5100|00000000 c0000638 00000000 00000000 
R;0x481c5110|00000030 09110813 00000000 00000000 
R;0x481c5120|00040013 00000320 04000000 00000000 
R;0x481c5130|00000000 c0000630 00000000 00000000 
R;0x481c5140|00000030 08110811 00000000 00000000 
R;0x481c5150|00020013 00000320 08000000 00000000 
R;0x481c5160|00000000 c0000638 00000000 00000000 
R;0x481c5170|00000030 08110811 00000000 00000000 
R;0x481c5180|00040013 00000320 08000000 00000000 
R;0x481c5190|00000000 c0000638 00000000 00000000 
R;0x481c51a0|00000030 09110813 00000000 00000000 
R;0x481c51b0|000a0013 0000021c 04000000 00000000 
R;0x481c51c0|00000000 c0000630 00000000 00000000 
R;0x481c51d0|00000030 08110811 00000000 00000000 
R;0x481c51e0|00080013 00000252 08000000 00000000 
R;0x481c51f0|00000000 c0000638 00000000 00000000 
R;0x481c5200|00000030 09910812 00000000 00000000 
R;0x481c5210|00050013 00000174 08000000 00000000 
R;0x481c5220|00000000 e0000161 00000000 00000000 
R;0x481c5230|00000030 08110811 00000000 00000000 
R;0x481c5240|00020013 000001f4 08000000 00000000 
R;0x481c5250|00000000 c0000638 00000000 00000000 
R;0x481c5260|00000030 291b0813 00000000 00000000 USBPLL_CLKCTRL Register (offset = 264h) [reset = 914824h] 28-24 NWELLTRIM R/W 0h Trim values for the PLL
R;0x481c5270|00050013 000003c0 04000000 00000000 
R;0x481c5280|00000000 c0000630 00000000 00000000 
R;0x481c5290|00000030 08110811 00000000 00000000 
R;0x481c52a0|00020013 00000320 04000000 00000000 
R;0x481c52b0|00000000 c0000630 00000000 00000000 
R;0x481c52c0|00000000 00000000 00000000 00000000 
R;0x481c52d0|00000000 00000000 000000a8 00000000 
R;0x481c52e0|09240924 00000000 00000000 00000000 
R;0x481c52f0|00000000 00000000 00000000 00000000 

PRCM Peripheral Registers CM_ALWON
R;0x48181500|00000000 00000000 00000000 00000000 
R;0x48181510|00000000 00000000 00000000 00000000 
R;0x48181520|00000000 00000000 00000000 00000000 
R;0x48181530|00000000 00000000 00000000 00000000 
R;0x48181540|00030000 00030000 00030000 00030000 
R;0x48181550|00000002 00000002 00000002 00030100 UART0,1,2
R;0x48181560|00030100 00000002 00030000 00000002 
R;0x48181570|00030000 00030000 00030000 00030000 
R;0x48181580|00000002 00030000 00000002 00000002 UART3,4,5
R;0x48181590|00000002 00030000 00030000 00030000 
R;0x481815a0|00070000 00000000 00030000 00000000 
R;0x481815b0|00030000 00000002 00030000 00030000 
R;0x481815c0|00030000 00000002 00000002 00000000 
R;0x481815d0|00000002 00000002 00040002 00000002 
R;0x481815e0|12500302 00000002 00000002 00000002 
R;0x481815f0|00000002 00030000 00030000 00030000

What is the wrong? If you have some information for this symptom, please let me know.

Best regards,

Michi

over 12 years ago

0 Biser Gatchev-XID over 12 years ago

TI__Guru**** 393215 points

Hi Michi,

I don't see how stop bit duration can influence UART communications (when it's longer than expected, of course). Could this be some inter-character delay, caused by software/processor interconnects/interrupt priorities etc.? In any case, with a "longer" stop bit your customer should have no trouble with communications. All UART's resync on every start bit falling edge.

Best Regards

Biser

0 Michi Yama over 12 years ago in reply to Biser Gatchev-XID

Guru 10030 points

Dear Biser-san,

Thank you for your reply.

This problem have benn solved by cvustomer. The cause of this problem was customer board isssue.

Your quick reply was very helpful for me. I appreciate your support.

Best regards,

Michi

Processors

Processors forum

AM387x UART3 problem?