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Can I connect multiple OMAP3 SoCs using a GPMC bus?

Jong-Woon Yoo
Prodigy 60 points

Hi all,

I'm trying to build a system shown below:

The FPGA manages various sensors connected to it and exposes sensor data to OMAPs. There could be several options to connect the OMAPs and FPGA but I believe the GPMC will be the best solution for this purpose as the FPGA can be shown as a shared memory device. The GPIO lines probably can be used to control bus access. You can find my previous post about this architecture here.

One thing that is not clear to me is wheather I can connect the all GPMC signals from multiple OMAPs to a single bus as shown in the figure above or not. Some pins, such as gpmc_a or gpmc_ncs, seem to be output-only and I'm worried about connecting these signals together would make collisions and the system unstable.

Even though I can make only one OMAP access the bus at a time using GPIO, but if other SoCs maintain their signal to output pins, it will cause problem. I'm carefully reading the TRM and datasheet but it is hard to find how these pins behave if they are set not to generate output. If the pins act as high-impedance, it will probably OK. But if the GPMC pins are designed to remain their state, it will cause collisions.

I am looking forward to hearing from you experts.

- Jongwoon

 

 

 

 

  • 0
    TI__Guru 65405 points

    Hi Jong,

    After discussing your issue with with our experts I receive the following advice:

    If FPGA is the access manager/scheduler and we can avoid timing windows overlap, I guess that we can may be put the 3 others GPMC Outputs in High impedance from a GP Input of the 3 OMAPs not interacting with the FPGA and not using other components on the GPMC. It is effectively designed to interface with several memories not sharing several OMAPs.

    BR

    Tsvetolin Shulev

  • 0 in reply to Cvetolin Shulev-XID
    Prodigy 60 points

    Hi Tsvetolin,

    Thank you very much for your reply. But it's still unclear to me how I can put the GPMC outputs in high impedance. Do you mean that (1) the GPMC outputs are already implemented to operate in tri-state manner so that they automatically go to high impedance state after a memory operation, (2) we can put them in high impedance by software, or (3) we can place external tri-state buffers (hardware chips) between the GPMC outputs and the bus? In cases of (1) and (2), we may not need additional component between the OMAPs and the bus. Otherwise, high speed tri-state buffers should be placed between the OMAPs and the bus.

    Once again, thank you in advance for any help.

    Best regards,

    Jongwoon 

  • 0 in reply to Jong-Woon Yoo
    Guru 31670 points

    Jongwoon,

    In the control pad registers you can configure the mux mode setting to mode 7 (safe mode for the pins that you want). But there is again one problem. For gpmc_cs0 its not defined.