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C5535 config for SPI, I2S2 and 7 GPIOs

Nicolas Boulot
Intellectual 330 points

Hello,

I would like to know what is the eBSR register configuration to be able to use SPI (with 2 CS), I2S2 and 7 GPIOS and 1 GPAIN.

It seems that I never can use more than 6 GPIOs at the same time without reconfiguring this eBSR register.

Thanks.

Nicolas

  • 0
    TI__Mastermind 30110 points

    Hi Nicolas,

    EBSR PPMODEs 1 and 6 route SPI + 4 CS, I2S2, 6 GPIOs, and either UART or I2S3 to the parallel port pins.

    Also available...

    Serial Port 0 muxes I2S0, SD0, and 6 GPIOs - GP[5:0]

    Serial Port 1 muxes I2S1, SD1, and 6 GPIOs - GP[11:6]

    Configure SP1MODE or SP0MODE bits to 2 (0x10) for GPIO routing.

    Refer to Table 4-9. EBSR Register Bit Descriptions, Table 4-10, and Table 4-11 in the C5535 datasheet

    Hope this helps,
    Mark

  • 0 in reply to Mark M
    Intellectual 330 points

    Hi Mark,

    Thanks for this fast answer. In fact using EBSR we will find the config that allows our spec.

    Otherwise, can you please comment the fact that it is possible to change or not the EBSR register after boot ?

    This is not so clear in the C5535 (page 94).

    Thanks.

    Nicolas

  • 0 in reply to Nicolas Boulot
    TI__Mastermind 30110 points

    Hi Nicolas,

    See http://e2e.ti.com/support/dsp/tms320c5000_power-efficient_dsps/f/109/p/220761/777934.aspx#777934

    Yes it is possible to change the EBSR register when the applicatuion is running, but you must clock gate each peripheral before the change and then reset each peripheral after the change.

    See 4.6.1 External Bus Selection Register (EBSR) in http://www.ti.com/lit/ds/symlink/tms320c5535.pdf

    "Before modifying the values of the external bus selection register, you must clock gate all affected peripherals through the Peripheral Clock Gating Control Register. After the external bus selection register has been modified, you must reset the peripherals before using them through the Peripheral Software Reset Counter Register."

    Peripheral Clock Gating Control Registers - PCGCR1 and PCGCR2 [1C02h and 1C03h]

    Peripheral Reset Control Register - PRCR [1C05h]

    Regards,
    Mark