PCIe boot mode for the C6678

HI Marcus,

Here are the answers

So the questions are:

(1)    What are the default values for Table 3-12 if PCIe boot mode is selected directly (no I2C)?

<AVM> Yes, you do not need I2C. We were going into IBL to fix a PLL issue we had in Silicon version 1.0. If you  have the PG2.0 version, you do not need to worry.

(2)    Are the window sizes listed in Table 3-15 in megabytes? (assume so)

<AVM> Yes.

(3)    If we don’t like the default values, is it possible to use the I2C slave boot mode to configure the DSP using our system processor (with PCIe as the extended boot mode (Table 3-20))?  It looks like it.

<AVM>Yes that is always possible.

(4)    If there is any additional sample code or documentation for the PCIe / I2C boot modes, that would be useful.

<AVM> as of now unfortunately no.

Also the port is always configured as 2 lanes and the link rate is option is to accomodate PCI vs PCIe devices. If you connect to PCIe RC, the link automatically updates to 5Gbps.

Thanks,

Arun.

Arun,

Thanks for your help. The customer will be using PG2.0 silicon so we don't have an issue with the IBL for the PLL fix. The concern is that the document calls out table 3-12 for the default settings but then provides the registers without their default values. Do we have documented what each register is set to in ROM?

Arun,

Response from customer:

This answered most of my questions, although it would be nice to know the default values in Table 3-12 (the second reply in the thread asked that question).

One followup question:

Will the default PCIe bootload mode work in 5 Gb/s mode with a 100 MHz PCIECLK?  sprabi2b (HW Design guide) has 156.25 MHz as the “recommended” PCIe reference clock, but we would prefer to use 100 MHz, the PCIe standard.

Thanks

Marcus

Hi Michael,

I just mentioned that you can set the values through I2C or use the default values instead. but it is not a bad idea to publish the default values. Let me see if I can get it to you. I am on Time Bank today. I can get the values tomorrow.

Hi Marcus,

From boot prespective they can use. I have asked HW expert to comment on the design guide claim. 

Thanks,

Arun.

The PCIe interface will operate at 5Gb/s using a 100MHz clock for PCIECLKP/N as long as that clock meets the jitter requirements presented in the Hardware Design Guide.  The higher clock speed is recommended because higher reference clock speeds have less stringent jitter requirements and because 156.25MHz is a common frequency with the other serdes interfaces on the C6678.  100MHz has been tested and characterized for PCIe to meet the PCIe specification and to allow the use of the common backplane clock found on the PCIe connector. 

Arun,

Can you send the documented default values to both Michael and myself?

Thanks

Response from customer:

Arun has been slightly missing the intent of my question.

 I understood that the HW was capable of supporting a 100 MHz reference clock, although it is always appreciated to have solid confirmation directly from an expert.  The fuzzy issue is whether the *default* PCIe boot mode configuration values will work with 100 MHz.  Since we don’t know what the defaults are for Table 3-12, this seems difficult to predict.  If it is not supported, we’ll have to budget more time to add the I2C boot mode option in the HW and also do some software development to dual-boot it (along with trying to understand how that all works, which is moderately complicated with various tables, sequences, etc).

 Offset 18 in Table 3-12 has:

Reference clock:  Reference clock frequency, in units of 10 kHz. Value values are 10000 (100 MHz), 12500 (125 MHz), 15625

(156.25 MHz), 25000 (250 MHz) and 31250 (312.5 MHz). A value of 0 means that value is already in the SerDes

cfg parameters and will not be computed by the boot ROM.

Here is the default values for PCIe Boot.

Customer Response:

Thanks Marcus (and to Arun).

It looks like the default reference clock (refClock10kHz) is set to 100 MHz, and the SerDes config registers are set for two lane operation starting at 2.5 Gb/s rate.  I am going to assume that Arun is correct and that it will negotiate up to 5 Gb/s after the initial G1 2.5 Gb/s link is established.

 I’m not quite sure why the serdesCfgLane0Lsw and serdesCfgLane1Lsw registers don’t quite match the sprugs6b listed defaults (clock data recovery enable field), but since those bits are undocumented, I’ll just consider them as don’t cares.

 I’ll still ask the HW group to hook up the I2C lines as a backup, but we’ll hope for the best and not do any SW development on the I2C pre-boot process.