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can't get TX data out of the McASP - C6748

Robert Wolfe
Mastermind 7860 points
Other Parts Discussed in Thread: OMAP-L138

Hello,

I’m having difficulty getting data out of the McASP TX pin.  Specifically, I’m using AXR11 for that purpose.  In the McASP interrupt, I’m getting the XRDY indication each time, from the serializer (11).  When it indicates ready, I then load in the latest RX data into RX (MCASP_CTRL->XBUFF11), which is a 32 bit value that represents a signal generator sine wave input, sampled at 12.5 Khz.  So the TX serializer must be thinking the data is going out, else it wouldn’t keep setting XRDY to true?  But yet when scoping pin AXR11, I never see anything going out.  However, I can put that pin into GPIO mode, and toggle it, and see it on the scope.  So it’s not being held high or low.

I’m kind of out of things to look at to debug this, and would appreciate any suggestions/points.

Robert

  • 0
    TI__Guru*** 125430 points

    A really common reason for not having data on the transmit side is due to underflow.  The McASP is incredibly picky when it comes to an underflow.  Once you've underflowed it will output zeros and the only way to recover is to reset/reinitialize the peripheral.  Make sure you are following the initialization procedure PRECISELY.  The interrupt should be enabled such that the transmitter has been serviced (and continues to be serviced) before you fully enable the McASP.  So if for example you are doing this initialization in main() prior to enabling GIE then you might not ever service the McASP and you'll immediately underflow.

  • 0 in reply to Brad Griffis
    Mastermind 7860 points

    You were correct sir ;)  There was underflow.  So I went through my McASP initialization with a fine tooth comb, including making sure that it matched the prescribed initialization and start-up sequence *exactly* (Section 2.4.1.2 in SPRUFM1 for C6748).  And now I have transmit data out of the TX.  Since I’m just routing the incoming RX to TX, I can correlate the 2 on a scope.

    Thanks,

    Robert

  • 0 in reply to Robert Wolfe
    Prodigy 230 points

    Robert, we are having the same problem with not getting data out of the TX line for MCaSP. Our underflow bit does not seem to be set, we get clocks and frame sync. Would it be possible for you to post your Mcasp setup or point out the part of (Section 2.4.1.2 in SPRUFM1 for C6748) that you changed to get it working.

     

    Any help is much appreciated.

     

    Thanks, John

  • 0 in reply to John Bolton82404
    Mastermind 7860 points

    Hi John,

    That problem was a while back, when I was deep in it. Now that time has passed, some of the details are not as apparent. But while the end result may be the same, i.e. no TX, it appears to be a different problem, since I definitely had an underflow bit set. About 2.4.1.2 in SPRUFM1, I recall going through it with a fine tooth comb, and ensuring that I was doing all steps exactly as indicated. It’s a bit complicated, so you have to really focus in, and double/triple check that your application is following the exact sequencing.

    The other thing that helped is that I started out with some TI examples for the OMAP-L138 development board we originally used, before going to target. Pretty sure they’re free and available on a TI website as part of the CSL 2.0 (sorry, I don’t recall where). If needed, I’ve attached the mcasp source file from it.

    Lastly, if still struggling, I’d encourage you to start a new E2E thread (likely to get more visibility that way).

    Regards,

    Robert

    Fullscreen 8345.mcasp.c Download 
    //Project  Name: quickStartOMAPL1x McASP Chip Support Library Example
//Texas Instruments Device Platform: Logic Product Development OMAP-L138 Experimentor Kit
//Copywrite (c) 2011 Texas Instruments Incroporated

/*===============================================================*/
/****************************LICENSE *****************************/
/*===============================================================*/
/*
 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.*/


//*==================================================*/
//********************Includes *********************/
//*==================================================*/
//*Non-DSP/BIOS5 Header Files*/
#include <ti/pspiom/cslr/tistdtypes.h>	
#include "mcasp.h"



//==================================================/
//***************Function Prototypes ***************/
//==================================================/
void McASPInit(void);
void McASPStart(void);
void McASPStart(void);



//==================================================/
//*********Global Variable Instantiations **********/
//==================================================/

//McASP0 Control Registers
CSL_McaspRegsOvly mcaspRegs = (CSL_McaspRegsOvly) CSL_MCASP_0_CTRL_REGS;	//OMAP-L138 McASP Configuration Register Pointer Instance

//McASP AFIFO Control Registers
CSL_AfifoRegsOvly afifoRegs = (CSL_AfifoRegsOvly) CSL_MCASP_0_FIFO_REGS;

//McASP DMA Port Registers
CSL_AdataRegsOvly adataRegs = (CSL_AdataRegsOvly) CSL_MCASP_0_DATA_REGS;


//==================================================/
//**********Functions ******************************/
//* This function is used to initialize the McASP*/
//==================================================/

//Notes: On Logic 1013527 Baseboard Hardware Mapping
//  AIC BCLK: connected to M_ACLKX/GPIO[14]
//  AIC WCLK: connected to M_AFSX/GPIO[12]
//  AIC DIN:  connected to M_AXR11 (OMAP-L138 Tx)
//  AIC DOUT  connected to M_AXR12 (OMAP-L138 Rx)
//  AIC MCLK  connected to M_AHCLKX (connected to 24.576MHz XTAL)

//OMAP-L138 Clocking Configuration
//AHCLKX -> External
//ACLKX  -> Internal / -> AHCLK/8
//AFSX   -> Interal -> Auto Generated by FS Gen.


void McASPInit(void)
{
	
/*This function will be called by Main to Initialize the McASP */
/* Although this configuration can be done completely by hand, we chose to use the 
 * OMAP-L138 Chip Support Library (CSL) because those functions presumably already
 *  work and are tested*/

	
//Initialize the McASP Registers for use on the LogicPD OMAP-L138 SOM/Baseboard.

/* The following steps are required to properly configure the McASP via the OMAP-L138 McASP User's Guide
* [1] Reset McASP to default Values by writting GBLCTL = 0
*/ 


 /* Put McASP in Reset by programming the global control registers */
	//Keep all Tx Clocks in Reset
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_XFRST, RESET);	
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_XSMRST, RESET);
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_XSRCLR, CLEAR);		
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_XHCLKRST, RESET);		
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_XCLKRST, RESET);
	
	//Keep all Rx Clocks In Reset
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_RFRST, RESET);
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_RSMRST, RESET);
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_RSRCLR, CLEAR);
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_RHCLKRST, RESET);
	CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_RCLKRST, RESET);


/* [2] Configure the McASP Audio FIFO.
 * 		[a] Write FIFO
 * 			 - If Write FIFO will not be enabled, clear the FIFO Enable Bit
 * 			 - If Write FIFO is enabled, it should not be enabled until all other FIFO 
 *             bits are configured
 * 		[b] Read FIFO
 * 			 - If Read FIFO will not be enabled, clear the FIFO Enable Bit
 * 			 - If Read FIFO is enabled, it should not be enabled until all other FIFO 
 * 
 */
 
 	/* Disable Write FIFO */
 		
 	// For now, both the Rx and Tx AFIFO's will be disabled, because the McASP is the only 
 	//peripheral that is being services by the DSP. If additional peripheral are added in later, 
 	//this may be changed to include both the Rx / Tx FIFO's	
 		
	//Disable Tx FIFO
	CSL_FINST(afifoRegs->WFIFOCTL, AFIFO_WFIFOCTL_WENA, DISABLED);
	
	//Disable Rx FIFO
	CSL_FINST(afifoRegs->RFIFOCTL, AFIFO_RFIFOCTL_RENA, DISABLED);
	
 
 /* [3] Configure all McASP registers except GBLCTRL in the following Order
  * 	[a] Receive Registers: If external clocks are used, they must be running already for proper synchronization
  *         of the global control registers
  * 		
  * 		Note:
  * 		TLV320AIC3106 is simply a slave ADC/DAC the Tx clocks will be synchronized with the Rx clocks. */
  
  
	/* Recieve Serializer */  	
  	/* 31   30    29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10      9        8      7       6    5     4    3     2     1   0 */                    
	/*MSb (MSb-1)        --Audio Word--                                          (LSb+1)  LSb    Mask     Mask Mask Mask  Mask  Mask Mask Mask */
  
  
  	/* Recieve Bit Stream Format Register */
	
	//Configure the receive bit stream for 32 bit I2S.
	CSL_FINST(mcaspRegs->RFMT, MCASP_RFMT_RDATDLY, 1BIT);		//Ignore First Bit due to I2S
	
	CSL_FINST(mcaspRegs->RFMT, MCASP_RFMT_RRVRS, MSBFIRST);
	
	//Pad Unused Bits with value in bit 0
	CSL_FINST(mcaspRegs->RFMT, MCASP_RFMT_RPAD, ZERO);
	
	//32 bit slot size, though only 24 bit word size
	CSL_FINST(mcaspRegs->RFMT, MCASP_RFMT_RSSZ, 32BITS);
	
	
	//No Rotation needed
	CSL_FINST(mcaspRegs->RFMT, MCASP_RFMT_RROT, NONE);
	
	//Read XRBUF[n] on the Peripheral Configuration Port  (For Now -> May change to the DMA Later)
	CSL_FINST(mcaspRegs->RFMT, MCASP_RFMT_RBUSEL, VBUS);
  
  
  
  
  
	/* Recieve Format Unit Bit Mask Register */
	
	//Mask Off Unused Bits -> For Now, well leave all unmasked -> May change later.
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK31, NOMASK);	//Audio Data MSB	
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK30, NOMASK);	//Audio Data MSB-1
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK29, NOMASK);   
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK28, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK27, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK26, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK25, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK24, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK23, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK22, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK21, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK20, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK19, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK18, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK17, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK16, NOMASK);	//Audio Data Bit LSB (16 bit)
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK15, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK14, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK13, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK12, NOMASK);	//Audio Data Bit LSB (20 bit)
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK11, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK10, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK9,  NOMASK);		
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK8,  NOMASK);	//Audio Data LSB (24 bit)
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK7,  NOMASK);		
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK6, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK5, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK4, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK3, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK2, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK1, NOMASK);
	CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK0, NOMASK);
	
	

	

/* Receive Frame Sync Control Register */
	
	//Configure Frame Sync for 2 Channel TDM
	CSL_FINST(mcaspRegs->AFSRCTL, MCASP_AFSRCTL_RMOD, I2S);
	//Configure Frame Sync to last length of word
	CSL_FINST(mcaspRegs->AFSRCTL, MCASP_AFSRCTL_FRWID, WORD);
	//Configure Frame Sync for internal generation
	CSL_FINST(mcaspRegs->AFSRCTL, MCASP_AFSRCTL_FSRM, INTERNAL);
	//Configure Frame Sync that falling edge starts new channel for I2S
	CSL_FINST(mcaspRegs->AFSRCTL, MCASP_AFSRCTL_FSRP, FALLINGEDGE);
	
	
	
	/* Receive Bit Clock Control Register */
	//Sample bit on Rising Edge of ACLKR
	CSL_FINST(mcaspRegs->ACLKRCTL, MCASP_ACLKRCTL_CLKRP, RISINGEDGE);
	//Clock Generated by OMAP-L138
	CSL_FINST(mcaspRegs->ACLKRCTL, MCASP_ACLKRCTL_CLKRM, INTERNAL);
	CSL_FINS(mcaspRegs->ACLKRCTL, MCASP_ACLKRCTL_CLKRDIV, 0); 			//Irrelvant when ASYNC = 0
	
	
	/*Receive High Frequency Clock Control Register (Master Clock)*/
		//Irrelvant when ASYNC = 0
		
	/*Receive TDM Time Slot Register */
	//Slots 31-2 Inactive
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS31, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS30, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS29, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS28, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS27, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS26, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS25, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS24, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS23, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS22, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS21, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS20, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS19, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS18, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS17, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS16, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS15, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS14, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS13, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS12, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS11, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS10, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS9, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS8, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS7, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS6, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS5, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS4, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS3, INACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS2, INACTIVE);
	//Slots 0,1 Active for I2S
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS1, ACTIVE);
	CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS0, ACTIVE);
	
	/* Receiver Interrupt Control Register */

	//Disable Start of Frame Interrupt
	CSL_FINST(mcaspRegs->RINTCTL, MCASP_RINTCTL_RSTAFRM, DISABLE);
	//Disable Data Read Interrupt
	CSL_FINST(mcaspRegs->RINTCTL, MCASP_RINTCTL_RDATA, DISABLE);
	//Disable Recive Last Time Slot Interrupt
	CSL_FINST(mcaspRegs->RINTCTL, MCASP_RINTCTL_RLAST, DISABLE);
	//Disable DMA Error Interrupt
	CSL_FINST(mcaspRegs->RINTCTL, MCASP_RINTCTL_RDMAERR, DISABLE);
	//Disable Clock Failure Error Interrupt
	CSL_FINST(mcaspRegs->RINTCTL, MCASP_RINTCTL_RCKFAIL, DISABLE);
	//Disable Unexpected FrameSync Error Interrupt
	CSL_FINST(mcaspRegs->RINTCTL, MCASP_RINTCTL_RSYNCERR, DISABLE);
	//Disable Reciever Overrun Error Interrupt
	CSL_FINST(mcaspRegs->RINTCTL, MCASP_RINTCTL_ROVRN, DISABLE);


  	//Recieve Clock Check Control Register
 		//Since Rx Clock is synchronized with Tx Clock, 
 		//No need to configure Rx Clock Check Circuit - because
 		//fail to Tx Clock will propogate in fail to Rx clock


  /* 	[b] Transmit Registers: If external clocks are used, they must be running already for proper synchronization
  *         of the global control registers */
  
  
  
  	/* Recieve Serializer */
	
	//Data Aligment Recieved from DSP -> Echo of McASP Rx
	/* 31      30    29    28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10   9       8      7     6 5 4 3 2 1 0 */                    
	/* Delay   MSb (MSb-1)                                                          LSb+1)  LSb  */

	//  ^
	//  |
	// (From I2S Protocol)		
	

  	/*Transmit Format Unit Bit Mask Register */
	//Keep All Bits unmaksed 
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK31, NOMASK);		//Audio Data Bit MSB
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK30, NOMASK);		//Audio Data Bit MSB-1	
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK29, NOMASK);			
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK28, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK27, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK26, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK25, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK24, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK23, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK22, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK21, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK20, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK19, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK18, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK17, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK16, NOMASK);		//Audio Data Bit LSB (16 bit)
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK15, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK14, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK13, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK12, NOMASK);		//Audio Data Bit LSB (20 bit)
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK11, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK10, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK9, NOMASK);		//Audio Data Bit LSB +1 
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK8, NOMASK);		//Audio Data Bit LSB (24 bit)	
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK7, NOMASK);				
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK6, NOMASK);			
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK5, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK4, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK3, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK2, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK1, NOMASK);
	CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK0, NOMASK);
	
		
	
	CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XDATDLY,  0BIT);		//For Echo, McASP has already delayed the 1 bit, 
												//so for a direct copy, do not delay another bit
	CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XRVRS,    MSBFIRST);
	CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XPAD, 	ZERO);
	CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XSSZ, 	32BITS);
	CSL_FINS(mcaspRegs->XFMT, MCASP_XFMT_XPBIT, 	0);
	CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XROT,	NONE);
	CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XBUSEL, 	VBUS);	

	/*Transmit Frame Sync Control Register */
		//Frame Sync is configured for I2S
	CSL_FINST(mcaspRegs->AFSXCTL, MCASP_AFSXCTL_XMOD, I2S);
		//Frame Sync Length is Word
	CSL_FINST(mcaspRegs->AFSXCTL, MCASP_AFSXCTL_FXWID, WORD);
		//Frame Sync is internally generated by XCLK
	CSL_FINST(mcaspRegs->AFSXCTL, MCASP_AFSXCTL_FSXM, INTERNAL);
		//Falled Edige indicates beginning of new word
	CSL_FINST(mcaspRegs->AFSXCTL, MCASP_AFSXCTL_FSXP, FALLINGEDGE);
	
	/* Transmit Clock Control Register */
	
	/* ACLKX = 3.072MHz = 64Fs = 256Fs/4 */
	CSL_FINST(mcaspRegs->ACLKXCTL, MCASP_ACLKXCTL_CLKXP, RISINGEDGE);
	CSL_FINST(mcaspRegs->ACLKXCTL, MCASP_ACLKXCTL_ASYNC, SYNC);				//ACLKR / nACLKX
	CSL_FINST(mcaspRegs->ACLKXCTL, MCASP_ACLKXCTL_CLKXM, INTERNAL);
	CSL_FINS(mcaspRegs->ACLKXCTL, MCASP_ACLKXCTL_CLKXDIV, 7);
	
	
	/* Transmit High Frequency Clock Register*/
	// Generate High Frequency Clock Source Externally from 24.576MHz XTAL
	CSL_FINST(mcaspRegs->AHCLKXCTL, MCASP_AHCLKXCTL_HCLKXM, EXTERNAL);
	CSL_FINST(mcaspRegs->AHCLKXCTL, MCASP_AHCLKXCTL_HCLKXP, NOTINVERTED);
	
	// AHCLKX = 24.576MHz
	CSL_FINS(mcaspRegs->AHCLKXCTL, MCASP_AHCLKXCTL_HCLKXDIV, 0);
		
	
	

	/* Transmit TDM Time Slot Register */
	//32-2 should be inactive
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS31, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS30, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS29, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS28, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS27, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS26, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS25, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS24, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS23, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS22, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS21, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS20, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS19, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS18, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS17, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS16, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS15, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS14, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS13, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS12, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS11, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS10, INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS9,  INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS8,  INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS7,  INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS6,  INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS5,  INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS4,  INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS3,  INACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS2,  INACTIVE);
	//Active Slots 0/1 for I2S
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS1,  ACTIVE);
	CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS0,  ACTIVE);
	
	/*Transmit Interrupt Control Register */
	//Disable All Transmit McASP Interrupts
	CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XSTAFRM, DISABLE);
	CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XDATA,   ENABLE);
	CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XLAST,   DISABLE);
	CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XDMAERR, DISABLE);
	CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XCKFAIL, DISABLE);		
	CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XSYNCERR, DISABLE);		
	CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XUNDRN,  DISABLE);		
	
  
  	//Transmit Clock Check Control Register
  		
	//Set McASP Clock Zone Post Scaler
	
	//Note McASP is driven by SYSCLK2 which is SYSCLK/ which is a divide
	// by two of the main system clock 300/2 = (150MHz)
	CSL_FINST(mcaspRegs->XCLKCHK, MCASP_XCLKCHK_XPS, DIVBY4);
	
	//Set XMAX Value
		//Notes: Prescale by 4
		//150/4 = 37.5 MHz.
		
		//37.5MHz /24.576MHz (AUXCLK)  = 1.52587890625
		//32 Clock Counts * 1.52587890625 = 48.8 McASP System Clock Counts per every 32 AHCLKX
		//Counts
		
		//___________________________________________
		//32 ACLKs / 24.576MHz = 1.302uSec 
		
		//48 Clocks / 37.5 MHz = 1.28 uSec
		//49 Clocks / 37.5 MHz = 1.306uSec
		
		//___________________________________________
		//Check
		//1.28 uSec < 1.302uSec < 1.306uSec
		
		//Include clock count buffer of 1 CLOCK
		//So Configure XMIN to be Uint8 47 (0x2F)
		//   Configure XMAX to be Uint8 50 (0x32)
	
	CSL_FINS(mcaspRegs->XCLKCHK, MCASP_XCLKCHK_XMIN, 0x2F);	
	CSL_FINS(mcaspRegs->XCLKCHK, MCASP_XCLKCHK_XMAX, 0x32);

  	
  
  
  /* 

  * [c] Serializer Registers */
 		//We only care to configure those for Serialzer 11,12 in this example
 	 
 	 //Configure Serializer 11 to be a Transmit Serializer
  	CSL_FINST(mcaspRegs->SRCTL11, MCASP_SRCTL11_SRMOD, XMT);
  	 //Configure Serializer 13 to be a Transmit Serializer (digital loopback mode)
  	//CSL_FINST(mcaspRegs->SRCTL13, MCASP_SRCTL13_SRMOD, XMT);
  	
  	//Configure Serializer 12 to be a Recieve Serializer
	CSL_FINST(mcaspRegs->SRCTL12, MCASP_SRCTL12_SRMOD, RCV);
 
 
 /* 	[d] Global Registers: */
 
 		/* PFUNC Register */
			//Configure AHCLKX, ACLKX, AFSX, AXR11, AXR12 as McASP Pins vs. GPIO Pins
	CSL_FINST(mcaspRegs->PFUNC, MCASP_PFUNC_AFSX, MCASP);
	CSL_FINST(mcaspRegs->PFUNC, MCASP_PFUNC_AHCLKX, MCASP);
	CSL_FINST(mcaspRegs->PFUNC, MCASP_PFUNC_ACLKX, MCASP);
	CSL_FINST(mcaspRegs->PFUNC, MCASP_PFUNC_AXR11, MCASP);
	CSL_FINST(mcaspRegs->PFUNC, MCASP_PFUNC_AXR12, MCASP);	


		/* PDIR Register */
		//Configure the AHCLKX, ACLKX, AFSX, AXR11 as Output Pins to send Clocks/Data from TLV320AIC3106
	CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_AFSX, OUTPUT);
	CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_AHCLKX, INPUT);
	CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_ACLKX, OUTPUT);
	CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_AXR11, OUTPUT);

	
	//Configure AXR11 as Input to Get Data from TLV320AIC3106
	CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_AFSR, INPUT);
	CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_AHCLKR, INPUT);
	CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_ACLKR, INPUT);
	CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_AXR12, INPUT);

/* Digital Interface Tranmistter Control Regiser */

	//Disable DIT Portion of McASP
	CSL_FINST(mcaspRegs->DITCTL, MCASP_DITCTL_DITEN, DISABLE);
	
/* Digital Loopback Control Register*/

	//Configure Digital Loopback
	CSL_FINST(mcaspRegs->DLBCTL, MCASP_DLBCTL_DLBEN, DISABLE);
	CSL_FINST(mcaspRegs->DLBCTL, MCASP_DLBCTL_ORD, XMTODD);

	

	/* AMUTE Register */

/* The stat of this register doesn't matter on the OMAP-L138 baseboard
 * because the AMUTE pin is not connected to the TLV320AIC3106 Device */
 
	//Configure AMUTE Pin to drive when any Error Occurs
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_XDMAERR, DISABLE);
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_RDMAERR, DISABLE);
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_XCKFAIL, DISABLE);
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_RCKFAIL, DISABLE);
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_XUNDRN, DISABLE);
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_ROVRN, DISABLE);
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_XUNDRN, DISABLE);
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_ROVRN, DISABLE);
	
	//Disable AMUTEIN Pin to isolate from LogicPD HW status
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_INSTAT, INACTIVE);
	
	//Disable Drive on AMUTEOUT when AMUTEIN error is active
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_INEN, DISABLE);
	
	//Configure AMUTE Input Logic Level to High
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_INPOL, ACTHIGH);
	//Disable AMUTE PIN
	CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_MUTEN, DISABLE);
	
	
	/* Steps 4-11 Continued in McASPStart(); */

return;
}

void McASPStart(void){
	

 	/* [4] Start the respective High Frequency Serial Clocks
 	 * 		[a] Take the respective High Frequency Clocks out of reset
 	 *		[b] Read back from GBLTRL to ensure the bits to which you wrote are sucessfully latch in GBLCTL before you proceed
 	 */
 	 	if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XHCLKRST)!=CSL_MCASP_GBLCTL_XHCLKRST_ACTIVE){
 	 		
 	 		 //Start Transmit High Frequency clock if not active
 			 CSL_FINST(mcaspRegs->XGBLCTL, MCASP_XGBLCTL_XHCLKRST, ACTIVE);
 			 
 			//Stall until GBLCTL reads back to ensure it was latched by the logic
 	 		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XHCLKRST)!=CSL_MCASP_GBLCTL_XHCLKRST_ACTIVE);	

 	 	}

 	 	
 	 	 if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RHCLKRST)!=CSL_MCASP_GBLCTL_RHCLKRST_ACTIVE){
 
 			//Start Recieve High Frequency clock
 	 	  	CSL_FINST(mcaspRegs->RGBLCTL, MCASP_RGBLCTL_RHCLKRST, ACTIVE);
 	 	  	 
 	 	  	 //Stall until GBLCTL reads back to ensure it was latched by the logic
 	 		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RHCLKRST)!=CSL_MCASP_GBLCTL_RHCLKRST_ACTIVE);
 	 	}

 	 
 	 /* [5] Start the respective serial clocks
 	  * 		[a] Take the respective internal serial clock dividers out of reset
 	  * 		[b] Read by from GBLCTL to ensure the bits to which you wrote are succesfully latched*/
 	  
		if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XCLKRST)!=CSL_MCASP_GBLCTL_XCLKRST_ACTIVE){
 	 		
  		 	//Start Transmit High Frequency clock if not active
 		 	CSL_FINST(mcaspRegs->XGBLCTL, MCASP_XGBLCTL_XCLKRST, ACTIVE);
 			 
 			//Stall until GBLCTL reads back to ensure it was latched by the logic
 	 		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XCLKRST)!=CSL_MCASP_GBLCTL_XCLKRST_ACTIVE);
 	 	}

 	 	 if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RCLKRST)!=CSL_MCASP_GBLCTL_RCLKRST_ACTIVE){
 
 			//Start Recieve Serial Clock
 	 		CSL_FINST(mcaspRegs->RGBLCTL, MCASP_RGBLCTL_RCLKRST, ACTIVE);
 	 	  	 
 	 	  	 //Stall until GBLCTL reads back to ensure it was latched by the logic
 	 		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RCLKRST)!=CSL_MCASP_GBLCTL_RCLKRST_ACTIVE);
 	 	}

 	 	/* [6] Set Up data acquistion as required 
 	 	 * 		[a] If DMA is used to service the McASP, set up the data Acquisition as desired and start 
 	 	 *          the DMA
 	 	 * 		[b] If CPU interrupt is used to service the McASP, enable the transmit/recieve interrupt
 	 	 *          as required
 	 	 *      [c] If CPU pooling is used to service the McASP, no action is required in this step
 	 	 */
 	 	 
 	 	 	//For now we use CPU polling -> so no action is required
 	 	 	
 	 	 /* [7] Activate Serializers
 	 	  * 	[a] Before starting, clear the Tx/Rx Status registers by writting FFFF to them*/
 	 	
 	 	  	
 	 	  
 	 	  	mcaspRegs->XSTAT = 0x0000FFFF;
 	 	  	mcaspRegs->RSTAT = 0x0000FFFF;
 
 	 	  	
 	 	/*  	[b] Take the Serializers out of Reset
 	 	 * [c] Read back from GBLCTL to ensure the bits are latched  */  	
 	 	 
 	 	if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XSRCLR)!=CSL_MCASP_GBLCTL_XSRCLR_ACTIVE){
 
 			//Start Recieve Serial Clock
 	 		CSL_FINST(mcaspRegs->XGBLCTL, MCASP_XGBLCTL_XSRCLR, ACTIVE);
 	 	  	 
 	 	  	// Stall until GBLCTL reads back to ensure it was latched by the logic
 	 		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XSRCLR)!=CSL_MCASP_GBLCTL_XSRCLR_ACTIVE);
 	 	} 
 	 	
 	  	if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RSRCLR)!=CSL_MCASP_GBLCTL_RSRCLR_ACTIVE){
 
 			//Start Recieve Serial Clock
 	 		CSL_FINST(mcaspRegs->RGBLCTL, MCASP_RGBLCTL_RSRCLR, ACTIVE);
 	 	  	 
 	 	  	// Stall until GBLCTL reads back to ensure it was latched by the logic
 	 		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RSRCLR)!=CSL_MCASP_GBLCTL_RSRCLR_ACTIVE);
 	 	} 	 	  
 
 	 	 
		/* [8] Verify that Tx Buffers are services. 
		 * 		[a] If DMA is used to service the McASP, the DMA auto services the McASP upon
		 * 			recieving AXEVT. Before proceeding, you should verify that the XDATA in XSTAT is clear
		 *   		to zero, indicating that the Tx buffers are already services by the DMA 
		 * 
		 *		[b] If CPU interrupt is used to service the McASP, ISRs is entered upon the AXINT interrupt.
		 *    		The interrupt service routing should service the XBUF registers. Before proceeding, clear
		 * 			the XDATA bit in the XSTAT
		 * 
		 * 		[c] If CPU Pooling is used to service the McASP, the XBUF Registers should be written to in this
		 * 			step */
		 
		 
		 	//Write Dummy Value of 0x00000000u to the XBUF11 (Tx Serializer)
		 	
		 
		 if(CSL_FEXT(mcaspRegs->XSTAT, MCASP_XSTAT_XDATA)==CSL_MCASP_XSTAT_XDATA_YES){
		 	mcaspRegs->XBUF11 = 0xFFFFFFFFu;
		 	//mcaspRegs->XBUF13 = 0x5555555Au;
		 }
		
		
		 	
		 
	

 /*[9] Release the State Machines from Reset */
 
 	 	if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XSMRST)!=CSL_MCASP_GBLCTL_XSMRST_ACTIVE){
 
 			//Start Recieve Serial Clock
 	 		CSL_FINST(mcaspRegs->XGBLCTL, MCASP_XGBLCTL_XSMRST, ACTIVE);
 	 	  	 
 	 	  	// Stall until GBLCTL reads back to ensure it was latched by the logic
 	 		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XSMRST)!=CSL_MCASP_GBLCTL_XSMRST_ACTIVE);
 	 	}
 	 	
 	 	if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RSMRST)!=CSL_MCASP_GBLCTL_RSMRST_ACTIVE){
 
 			//Start Recieve Serial Clock
 	 		CSL_FINST(mcaspRegs->RGBLCTL, MCASP_RGBLCTL_RSMRST, ACTIVE);
 	 	  	 
 	 	  	// Stall until GBLCTL reads back to ensure it was latched by the logic
 	 		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RSMRST)!=CSL_MCASP_GBLCTL_RSMRST_ACTIVE);
 	 	}
 
 




/* [10]. Release frame sync generators from reset. Note that it is necessary to release the internal frame sync
generators from reset, even if an external frame sync is being used, because the frame sync error
detection logic is built into the frame sync generator.
	a. Take the respective frame sync generator(s) out of reset by setting the RFRST bit for the receiver,
		and/or the XFRST bit for the transmitter in GBLCTL. All other bits in GBLCTL should be left at the
		previous state. 
	b. Read back from GBLCTL to ensure the bit(s) to which you wrote are successfully latched in
		GBLCTL before you proceed. */



 	 if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XFRST)!=CSL_MCASP_GBLCTL_XFRST_ACTIVE){
  			//Start Recieve Serial Clock
  		CSL_FINST(mcaspRegs->XGBLCTL, MCASP_XGBLCTL_XFRST, ACTIVE);
  	  	 
  	  	 //Stall until GBLCTL reads back to ensure it was latched by the logic
  		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XFRST)!=CSL_MCASP_GBLCTL_XFRST_ACTIVE);
  	}
  	
  	if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RFRST)!=CSL_MCASP_GBLCTL_RFRST_ACTIVE){
  			//Start Recieve Serial Clock
  		CSL_FINST(mcaspRegs->RGBLCTL, MCASP_RGBLCTL_RFRST, ACTIVE);
  	  	 
  	  	 //Stall until GBLCTL reads back to ensure it was latched by the logic
  		while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RFRST)!=CSL_MCASP_GBLCTL_RFRST_ACTIVE);
  	}

		






/* [11]. Upon the first frame sync signal, McASP transfers begin. The McASP synchronizes to an edge on the
frame sync pin, not the level on the frame sync pin. This makes it easy to release the state machine
and frame sync generators from reset.
a. For example, if you configure the McASP for a rising edge transmit frame sync, then you do not
need to wait for a low level on the frame sync pin

*/	
	

	
	

	return;	
}

void McASPStop(void){

	/* This function should be used to stop clocks in the reverse order
	 * from McASPStart */
	 
	return;	
}

void McASPEcho(void){
	/* This function is used to wait until a McASP Event comes in, 
	 * read the data and directly write it back out to the Codec */
	 
	 //Notes McASP Interrupts are still masked here so nothing should
	 //interrupt the CPU
	 
	 //RSYNC error is expected right away, but shouldn't occur after first event
	   		//because the clock references are internal and stable
  
 	return;
}

void McASPRestart(){
	
	if(mcaspRegs->GBLCTL == 0x00000000){
		
		McASPInit();
		McASPStart();
	}
	
	
}

     

  • 0 in reply to Robert Wolfe
    TI__Guru*** 125430 points

    You should also verify your pin muxing.  If pin muxing is not the issue please post a new thread.