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Other Parts Discussed in Thread: SYSCONFIG
Hi,
I am trying to use the OMAP4460 (Pandaboard) to drive RFBI output. It works fine if i configure it for LCD1 channel.
When i configure it through LCD2 channel, no FRAMEDONE2 interrupt and the pixel transaction is not getting completed.
I am using Linux kernel 3.3.
Regards,
Suresh
Hi Sareshkumar
I assume you are setting the bit DSS_CTRL[14] : RFBI_SWITCH
Could you please do a Register Dump for the Display Controller.
cat /sys/kernel/debug/omapdss/dss
cat /sys/kernel/debug/omapdss/dispc
Thanks
Rafael
Hi Rafael,
Thanks for the information.
I was not setting the RFBI_SWITCH correctly. Now I do get the FRAMEDONE2 interrupt but still the RFBI data line is not toggling.
I have set the pad configuration to RFBI. Let me know if I am missing anything else.
Here is the register dump
DSS_REVISION 00000040
DSS_SYSCONFIG 00000000
DSS_SYSSTATUS 00000001
DSS_CONTROL 0000c000
DISPC_REVISION 00000040
DISPC_SYSCONFIG 00002015
DISPC_SYSSTATUS 00000001
DISPC_IRQSTATUS 00000004
DISPC_IRQENABLE 0052d640
DISPC_CONTROL 00008002
DISPC_CONFIG 00000004
DISPC_CAPABLE 00000000
DISPC_LINE_STATUS 00000000
DISPC_LINE_NUMBER 00000000
DISPC_GLOBAL_ALPHA ffffffff
DISPC_CONTROL2 00000908
DISPC_CONFIG2 00000000
DISPC_DEFAULT_COLOR(LCD) 00000000
DISPC_TRANS_COLOR(LCD) 00000000
DISPC_SIZE_MGR(LCD) 00000000
DISPC_DEFAULT_COLOR(LCD) 00000000
DISPC_TRANS_COLOR(LCD) 00000000
DISPC_TIMING_H(LCD) 00000000
DISPC_TIMING_V(LCD) 00000000
DISPC_POL_FREQ(LCD) 00000000
DISPC_DIVISORo(LCD) 00040001
DISPC_SIZE_MGR(LCD) 00000000
DISPC_DATA_CYCLE1(LCD) 00000000
DISPC_DATA_CYCLE2(LCD) 00000000
DISPC_DATA_CYCLE3(LCD) 00000000
DISPC_CPR_COEF_R(LCD) 00000000
DISPC_CPR_COEF_G(LCD) 00000000
DISPC_CPR_COEF_B(LCD) 00000000
DISPC_DEFAULT_COLOR(TV) 00000000
DISPC_TRANS_COLOR(TV) 00000000
DISPC_SIZE_MGR(TV) 01df027f
DISPC_DEFAULT_COLOR(LCD2) 00000000
DISPC_TRANS_COLOR(LCD2) 00000000
DISPC_SIZE_MGR(LCD2) 01df027f
DISPC_DEFAULT_COLOR(LCD2) 00000000
DISPC_TRANS_COLOR(LCD2) 00000000
DISPC_TIMING_H(LCD2) 04f02f1f
DISPC_TIMING_V(LCD2) 00700303
DISPC_POL_FREQ(LCD2) 00000000
DISPC_DIVISORo(LCD2) 00010005
DISPC_SIZE_MGR(LCD2) 01df027f
DISPC_DATA_CYCLE1(LCD2) 00000000
DISPC_DATA_CYCLE2(LCD2) 00000000
DISPC_DATA_CYCLE3(LCD2) 00000000
DISPC_CPR_COEF_R(LCD2) 00000000
DISPC_CPR_COEF_G(LCD2) 00000000
DISPC_CPR_COEF_B(LCD2) 00000000
DISPC_OVL_BA0(GFX) ad800000
DISPC_OVL_BA1(GFX) ad800000
DISPC_OVL_POSITION(GFX) 00000000
DISPC_OVL_SIZE(GFX) 01df027f
DISPC_OVL_ATTRIBUTES(GFX) 02000190
DISPC_OVL_FIFO_THRESHOLD(GFX) 04ff04f8
DISPC_OVL_FIFO_SIZE_STATUS(GFX) 00000500
DISPC_OVL_ROW_INC(GFX) 00000001
DISPC_OVL_PIXEL_INC(GFX) 00000001
DISPC_OVL_PRELOAD(GFX) 00000100
DISPC_OVL_WINDOW_SKIP(GFX) 00000000
DISPC_OVL_TABLE_BA(GFX) 00000000
DISPC_OVL_BA0(VID1) 00000000
DISPC_OVL_BA1(VID1) 00000000
DISPC_OVL_POSITION(VID1) 00000000
DISPC_OVL_SIZE(VID1) 00000000
DISPC_OVL_ATTRIBUTES(VID1) 02018400
DISPC_OVL_FIFO_THRESHOLD(VID1) 00000000
DISPC_OVL_FIFO_SIZE_STATUS(VID1) 00000800
DISPC_OVL_ROW_INC(VID1) 00000001
DISPC_OVL_PIXEL_INC(VID1) 00000001
DISPC_OVL_PRELOAD(VID1) 00000100
DISPC_OVL_FIR(VID1) 04000400
DISPC_OVL_PICTURE_SIZE(VID1) 00000000
DISPC_OVL_ACCU0(VID1) 00000000
DISPC_OVL_ACCU1(VID1) 00000000
DISPC_OVL_BA0_UV(VID1) 00000000
DISPC_OVL_BA1_UV(VID1) 00000000
DISPC_OVL_FIR2(VID1) 04000400
DISPC_OVL_ACCU2_0(VID1) 00000000
DISPC_OVL_ACCU2_1(VID1) 00000000
DISPC_OVL_ATTRIBUTES2(VID1) 00000000
DISPC_OVL_PRELOAD(VID1) 00000100
DISPC_OVL_BA0(VID2) 00000000
DISPC_OVL_BA1(VID2) 00000000
DISPC_OVL_POSITION(VID2) 00000000
DISPC_OVL_SIZE(VID2) 00000000
DISPC_OVL_ATTRIBUTES(VID2) 02018400
DISPC_OVL_FIFO_THRESHOLD(VID2) 00000000
DISPC_OVL_FIFO_SIZE_STATUS(VID2) 00000800
DISPC_OVL_ROW_INC(VID2) 00000001
DISPC_OVL_PIXEL_INC(VID2) 00000001
DISPC_OVL_PRELOAD(VID2) 00000100
DISPC_OVL_FIR(VID2) 04000400
DISPC_OVL_PICTURE_SIZE(VID2) 00000000
DISPC_OVL_ACCU0(VID2) 00000000
DISPC_OVL_ACCU1(VID2) 00000000
DISPC_OVL_BA0_UV(VID2) 00000000
DISPC_OVL_BA1_UV(VID2) 00000000
DISPC_OVL_FIR2(VID2) 04000400
DISPC_OVL_ACCU2_0(VID2) 00000000
DISPC_OVL_ACCU2_1(VID2) 00000000
DISPC_OVL_ATTRIBUTES2(VID2) 00000000
DISPC_OVL_PRELOAD(VID2) 00000100
DISPC_OVL_BA0(VID3) 00000000
DISPC_OVL_BA1(VID3) 00000000
DISPC_OVL_POSITION(VID3) 00000000
DISPC_OVL_SIZE(VID3) 00000000
DISPC_OVL_ATTRIBUTES(VID3) 02018400
DISPC_OVL_FIFO_THRESHOLD(VID3) 00000000
DISPC_OVL_FIFO_SIZE_STATUS(VID3) 00000800
DISPC_OVL_ROW_INC(VID3) 00000001
DISPC_OVL_PIXEL_INC(VID3) 00000001
DISPC_OVL_PRELOAD(VID3) 00000100
DISPC_OVL_FIR(VID3) 04000400
DISPC_OVL_PICTURE_SIZE(VID3) 00000000
DISPC_OVL_ACCU0(VID3) 00000000
DISPC_OVL_ACCU1(VID3) 00000000
DISPC_OVL_BA0_UV(VID3) 00000000
DISPC_OVL_BA1_UV(VID3) 00000000
DISPC_OVL_FIR2(VID3) 04000400
DISPC_OVL_ACCU2_0(VID3) 00000000
DISPC_OVL_ACCU2_1(VID3) 00000000
DISPC_OVL_ATTRIBUTES2(VID3) 00000000
DISPC_OVL_PRELOAD(VID3) 00000100
DISPC_OVL_FIR_COEF_H_0(VID1) 00000000
DISPC_OVL_FIR_COEF_H_1(VID1) 00000000
DISPC_OVL_FIR_COEF_H_2(VID1) 00000000
DISPC_OVL_FIR_COEF_H_3(VID1) 00000000
DISPC_OVL_FIR_COEF_H_4(VID1) 00000000
DISPC_OVL_FIR_COEF_H_5(VID1) 00000000
DISPC_OVL_FIR_COEF_H_6(VID1) 00000000
DISPC_OVL_FIR_COEF_H_7(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_0(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_1(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_2(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_3(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_4(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_5(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_6(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_7(VID1) 00000000
DISPC_OVL_CONV_COEF_0(VID1) 0199012a
DISPC_OVL_CONV_COEF_1(VID1) 012a0000
DISPC_OVL_CONV_COEF_2(VID1) 079c0730
DISPC_OVL_CONV_COEF_3(VID1) 0000012a
DISPC_OVL_CONV_COEF_4(VID1) 00000205
DISPC_OVL_FIR_COEF_V_0(VID1) 00000000
DISPC_OVL_FIR_COEF_V_1(VID1) 00000000
DISPC_OVL_FIR_COEF_V_2(VID1) 00000000
DISPC_OVL_FIR_COEF_V_3(VID1) 00000000
DISPC_OVL_FIR_COEF_V_4(VID1) 00000000
DISPC_OVL_FIR_COEF_V_5(VID1) 00000000
DISPC_OVL_FIR_COEF_V_6(VID1) 00000000
DISPC_OVL_FIR_COEF_V_7(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_0(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_1(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_2(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_3(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_4(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_5(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_6(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_7(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_0(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_1(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_2(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_3(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_4(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_5(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_6(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_7(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_0(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_1(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_2(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_3(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_4(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_5(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_6(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_7(VID1) 00000000
DISPC_OVL_FIR_COEF_H_0(VID2) 00000000
DISPC_OVL_FIR_COEF_H_1(VID2) 00000000
DISPC_OVL_FIR_COEF_H_2(VID2) 00000000
DISPC_OVL_FIR_COEF_H_3(VID2) 00000000
DISPC_OVL_FIR_COEF_H_4(VID2) 00000000
DISPC_OVL_FIR_COEF_H_5(VID2) 00000000
DISPC_OVL_FIR_COEF_H_6(VID2) 00000000
DISPC_OVL_FIR_COEF_H_7(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_0(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_1(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_2(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_3(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_4(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_5(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_6(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_7(VID2) 00000000
DISPC_OVL_CONV_COEF_0(VID2) 0199012a
DISPC_OVL_CONV_COEF_1(VID2) 012a0000
DISPC_OVL_CONV_COEF_2(VID2) 079c0730
DISPC_OVL_CONV_COEF_3(VID2) 0000012a
DISPC_OVL_CONV_COEF_4(VID2) 00000205
DISPC_OVL_FIR_COEF_V_0(VID2) 00000000
DISPC_OVL_FIR_COEF_V_1(VID2) 00000000
DISPC_OVL_FIR_COEF_V_2(VID2) 00000000
DISPC_OVL_FIR_COEF_V_3(VID2) 00000000
DISPC_OVL_FIR_COEF_V_4(VID2) 00000000
DISPC_OVL_FIR_COEF_V_5(VID2) 00000000
DISPC_OVL_FIR_COEF_V_6(VID2) 00000000
DISPC_OVL_FIR_COEF_V_7(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_0(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_1(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_2(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_3(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_4(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_5(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_6(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_7(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_0(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_1(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_2(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_3(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_4(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_5(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_6(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_7(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_0(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_1(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_2(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_3(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_4(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_5(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_6(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_7(VID2) 00000000
DISPC_OVL_FIR_COEF_H_0(VID3) 00000000
DISPC_OVL_FIR_COEF_H_1(VID3) 00000000
DISPC_OVL_FIR_COEF_H_2(VID3) 00000000
DISPC_OVL_FIR_COEF_H_3(VID3) 00000000
DISPC_OVL_FIR_COEF_H_4(VID3) 00000000
DISPC_OVL_FIR_COEF_H_5(VID3) 00000000
DISPC_OVL_FIR_COEF_H_6(VID3) 00000000
DISPC_OVL_FIR_COEF_H_7(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_0(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_1(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_2(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_3(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_4(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_5(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_6(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_7(VID3) 00000000
DISPC_OVL_CONV_COEF_0(VID3) 0199012a
DISPC_OVL_CONV_COEF_1(VID3) 012a0000
DISPC_OVL_CONV_COEF_2(VID3) 079c0730
DISPC_OVL_CONV_COEF_3(VID3) 0000012a
DISPC_OVL_CONV_COEF_4(VID3) 00000205
DISPC_OVL_FIR_COEF_V_0(VID3) 00000000
DISPC_OVL_FIR_COEF_V_1(VID3) 00000000
DISPC_OVL_FIR_COEF_V_2(VID3) 00000000
DISPC_OVL_FIR_COEF_V_3(VID3) 00000000
DISPC_OVL_FIR_COEF_V_4(VID3) 00000000
DISPC_OVL_FIR_COEF_V_5(VID3) 00000000
DISPC_OVL_FIR_COEF_V_6(VID3) 00000000
DISPC_OVL_FIR_COEF_V_7(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_0(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_1(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_2(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_3(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_4(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_5(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_6(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_7(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_0(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_1(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_2(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_3(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_4(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_5(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_6(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_7(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_0(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_1(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_2(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_3(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_4(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_5(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_6(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_7(VID3) 00000000
Hi Sareshkumar
Please try setting the default color to something known, say blue
DISPC_DEFAULT_COLOR(LCD2) 000000FF
When all overlays are disabled, you should see the blue color.
Which brings me to the next point, you have not enabled any overlay to use LCD2.
GFX is the only one configured and DISPC_GFX_ATTRIBUTES[30:31] is 0, i.e primary LCD output selected.
Change it to 1. Secondary LCD selected.
Let me know how it goes.
Regards
Rafael
Also, remember that to enable LCD2, you need to set the DISPC_CONTROL2[0]
Hi Rafael,
Your suggestion seems to fix the issue. Though i have not verified with actual display. I am able verify the activity on the LCD port.
It took sometime for me to figure out where in linux driver to make these changes and hence the delay in response.
Thanks for your quick valuable inputs.
Regards,
Suresh
Hi,
I ran into another issue.
I am able to send the Pixel data through RFBI interface but the command write is not going through.
I found that the RFBI module is always in disabled state (RFBI_CONTROL[0] = 0)
It gets enabled only during pixel data transfer and gets disabled automatically after that.
I tried to change the idle mode register (RFBI_SYSCONFIG[3:4]) but no change is behavior.
Please let me know what am I missing.
Regards,
Suresh
Hi,
I am having a similar issue and I have looked at my DISPC registers and also I need to enabled LCD2 and set the overlay (GFX) to point to LCD2.
Can you describe what you did and where to set these registers in the Kernel Source?
Many Thanks,
Nigel
