Here is the assembly for the cache invalidate on the A8 in Cache_asm.asm:
ti_sysbios_family_arm_a8_Cache_invL1d__I
.asmfunc
add r1, r0, r1 ; calculate last address
bic r0, r0, #Cache_sizeL1dCacheLine - 1
; align blockPtr to cache line
invDCache_loop:
mcr p15, #0, r0, c7, c6, #1 ; invalidate single entry in DCache
add r0, r0, #Cache_sizeL1dCacheLine
; increment address by cache line size
cmp r0, r1 ; compare to last address
blo invDCache_loop ; loop if > 0
tst r2, #0x1 ; check if wait param is TRUE
mcrne p15, #0, r0, c7, c10, #4 ; drain write buffer
bx r14 ; return
.endasmfunc
Is it just me, or is the tst r2, #0x1 backwards? If you want to wait for the opperation to complete you would pass TRUE in, setting R2 to 1. This test instruction will say they are equal. However, the data syncronization instruction mcrne will execute if the test is not equal. This seems opposite from what was intended, Or am I missing something?
