L138 SPI Data Throughput

Using OMAPL138 SPI in slave mode or master mode? Have they looked at the datasheet for max clock rates supported for SPI?

All,

We've gotten more information from the customer.  Here's what they are requesting, the customer gave confusing information initially:

When connecting the THS1206 to the OMAP-L138, I’d like to set the FIFO threshold on the ADC to 8 or 12 and use its DATA_AV signal to trigger a DMA event.  What I am wondering is can/how do we setup a DMA such that it will wake up on every DATA_AV each time DMAing to sequential addresses.  We’d want it to do N many of these in a row before doing a ping-pong buffer flip.  This buffer flip event should also trigger an interrupt to the DSP (preferably such that it can release the IDLE instruction).  Are we asking too much of the DMA to be able to be configured as such?  I want to make sure we are not making incorrect assumptions before we get too far.  Nominally we don’t want the ARM to be the data pusher (I’d rather it not have to wake up on an interrupt from DATA_AV every time to queue a small DMA…I’d like it to be available to do some sort of processing if need be).

Thanks for the promote reply, I need something back as soon as possible!

Pete

Peter,

Sounds like your customer  is trying to implement a self chain where the DMA sequences through N 8 byte transfers in the first buffer and then would like to do the same on another buffer after getting an DMA transfer completion interrupt from the first buffer. This seems doable unless I am misinterpreting the requirement.

If you look at the EDMA examples provided here:

http://processors.wiki.ti.com/index.php/QuickStartOMAPL1x_rCSL

The requirement seems to be a combination of the self chain example and the ping pong example wherein only the timer interrupt event needs to be changed to the DATA_AV  triggering the first self chain transfer and the DMA transfer completion interrupt from the first self chain acting as the ping-pong buffer flip interrupt that Honeywell is looking for.

Let us know if there are any follow up questions.

Regards,

Rahul

Below is the excerpt from the customer email describing the use case in more detail.

In addition, the following thread is also referencing the same topic with the same customer.

I think what I’m looking for is just a little bit more complex.

The ADC will capture lets say 8 samples (I’m not 100% certain on if that’s 8 I/Q pairs, or 4 I/Q pairs…I still have a question on what that threshold means in dual channel mode on that ADC).  Those 8 samples are 12-bits each.  The DATA_AV signal will fire and should start a DMA automatically.  Then we want that event to happen N times.  After N times, we should have a buffer flip.

So to layout a more detailed example, lets assume N is perhaps 512.

Theory of operation: (I’ll paraphrase more as I go on but start a bit more verbose to explain what I’m thinking)

ARM processor queues DMA.

ADC captures 8 12-bit samples (which would be 16 bytes)

ADC triggers DATA_AV

EDMA transfers from ADC 8 16-bit words (bus width) into address A+0

ADC captures 8 12-bit samples

ADC triggers DATA_AV

EDMA transfers from ADC 8 16-bit words into address A+(8*2) (base address A continuing where the first DMA left off)

… repeats 510 more times …

DMA triggers interrupt to DSP for it to wake up from IDLE (or just executes and interrupt handler)

DMA flips buffers and begins using address B

for i = 0:511

                ADC captures 8 12-bit samples
                ADC triggers DATA_AV
                EDMA transfers from ADC 8 16-bit words into address B+(i*8*2)

DMA triggers interrupt to DSP

for i = 0:511

                ADC captures 8 12-bit samples
                ADC triggers DATA_AV
                EDMA transfers from ADC 8 16-bit words into address A+(i*8*2)

 

So I think what I’m asking for is another dimension to the transfer request without processor intervention.

Taking a figure out of the OMAP-L138 Technical Reference Manual, the below illustrates what I believe the customer is describing.  Section 18.2.2.2 of the TRM discusses the example of an AB-Synchronized transfer where ACNT=size of data (ie. 2 bytes), BCNT=line of samples (ie. 8 samples) and CCNT=size of buffer (ie. 512/8).

Based on this configuration, this should handle the "ping buffer" which is comprises the customer's buffer of 512 12-bit samples.  One parameter set (PaRAM set) should be able to handle this.  The completion of this PaRAM can generate an interrupt to the DSP.  In addition, the PaRAM set would also populate the Link address field to point to the next PaRAM set that would describe the "pong buffer".  If setup correctly, the EDMA PaRAM sets can be configured to have complete processor independence if desired.  The completion of each PaRAM set could generate an interrupt for the DSP to process each buffer, either "ping" or "pong".  The source address can be static, which would be the external ADC address and the destination address can be incremented after each datum transfer.

Section 18.2.3.7 discusses Linking transfers where the second sentence in the section talks about a ping-pong buffer as an example.

Hi Brandon,

Thanks for taking the effort of posting your analysis here of the customers usecase. Like you mentioned, I also believed that AB-synchronized transfers is what the customer is trying to implement based on Peter`s description. An example implementation of this is available in the QuickStart_rCSL package (the link to which has been provided in the wiki I had pointed earlier).

I would recommend the customer to look at that example.

Regards,

Rahul