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PLL multiplier minimum input frequency range (100MHz / 3 * 40 / 2 = 667MHz = DDR3-1333?)

Günter
Intellectual 460 points
What is the minimum allowed input frequency for the C665x PLL multiplier? Guess I use the minimum input frequency of 40MHz and divide with maximum PLLD=63. This would result in 40/64 = 0.625MHz fed to the multiplier, which seems to be too slow. A more realistic example is 100MHz input clock for DDR3 with PLLD =2 (divide by 3) resulting in 33MHz which can be multiplied to any of the required DDR-3 frequencies (400MHz, 533MHz, 666MHz). Are there any specs regarding allowed PLLD values at the specified input frequency range (40MHz to 312.5MHz) or are there any specs regarding allowed PLLM input frequency? Does the selection of extremely low multiplier frequency have any negative impact on PLL jitter? best regards Guenter
  • 0
    TI__Mastermind 30825 points

    Gunter,

    As long as you meet the input clocking frequency range and jitter spec of the input clock itself, the PLL can support the use of 63 as the divisor.  Of course you'd expect to need a multiplier with that such that it creates a realistic end frequency.

    An example of using this sort of range is the Automatic Main PLL settings w/ the bootstrapping for a device speed of 800MHz, with 122.88MHz input clock you have a PLLD of 47 and PLLM of 624. I used this as an example as it's a PLL example that's predefined and hard coded with our bootROM.  We don't have such an example for the DDR PLL, but they have the same jitter requirements.

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Intellectual 460 points
    At first look this sound quite good. So you have 122.88MHz divided by 48 (PLLD+1) resulting in 2.56MHz, then multiplied by 625 (PLLM+1) resulting in 1600MHz, probably divided by 2 using the PLL's post divider to give the final 800MHz. But meanwhile TI support pointed me to two statements in SPRABI2B, section 3.2: "The core PLL can be configured with multiplier values from ×1 to ×64 and any integer value in between as long as the PLL output frequency does not violate the maximum operating frequency for the C66x device." "The DDR3 PLL can be configured with multiplier values from ×20 to ×33 and any integer value in between (non fractional) as long as the PLL output frequency does not violate the maximum DDR3 output operating frequency for the C66x device." If the above statements means the PLLM bit field, then some of the main PLL settings supported by BOOTCONF pins would be way too high. If the above statement means the overall PLL multiplier (PLLD, PLLM and div_by_2), then some of the main PLL settings supported by BOOTCONF pins violate this rule by generating non-integer values. Anyway, now I'll use 66.67MHz input clock so I can stay within the 20...33 range for DDR3 PLL. Best regards, Guenter