Setting UART baud rate on 6657

Yes, it can go faster.  The UART belongs to clock domain SYSCLK7 which runs at CPU/6.  What's your CPU frequency?  The baud rate is determined through a combination of the UART's DLL, DLH, and OSM_SEL.  The difficulty is that as the desired baud rate gets larger it becomes more difficult to accurately divide down SYSCLK7 to achieve it.  See Table 2-1 "Baud Rate Examples for 150-MHz UART Input Clock and 16× Oversampling Mode" in the UART for some examples.  The clock generation is described in Section 2.1 "Clock Generation and Control" of that same document.

Keystone UART User Guide
http://www.ti.com/lit/sprugp1

We have a 100 MHz clock going to the DSP and then it's running at 1 GHz. So the SYSCLK7 would be ~166.66 MHz which is what the UART would run at.

If we set the OSM_SEL to 0 to select 16x oversampling and use a divisor value of 45, that will set the baud rate at 231481 kpbs. DLH would be set to 00 and DLL would be set to 2D. Does that look correct?

The description for DLH in Table 3-16 confused me since it says "Maximum baud rate is 128 kbps." That contradicts what was in table 2-1.

Kevin,

That comment was apparently a copy and paste error when using one of the catalog devices UG's as a template. 

Best Regards,

Chad

hi Chad,

Looking at the datasheet the UART timings do refer to the baud rate programmed (see page 200 of SPRS814A). Then looking at SPRUGP1 page 2-3 the maximum baud rate shown in table 2-1 is 3.0 MHz.
Could you please confirm it is the maximum baud rate that we specify (from the timing specification point of view)? If not what is the max?

It would make sense to have the Maximum programmable baud rate shown in the datasheet as it is done for AM3358 (see page 222 of SPRS717F).

Thanks and best regards,

Anthony