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L1PICR and L1PISAR register descriptions

Julxhino Gocllari
Prodigy 105 points

Does anyone know were I can find the register descriptions of the cache registers for the C672x family of DSPs, the data manual only says where they are located in the memory map, but it doesn't describe their bit maps.

  • 0
    TI__Guru 68920 points

    It looks like we missed documenting the register bit fields.

    The basic information from the internal CPU Megamodule spec is summarized below:

    L1PISAR is a single bit field bits 31:0 being the start address (byte address) of the block that should be invalidated from L1P Cache.

    L1PISAR should be programmed before L1PICR which is the Invalidate Control Register. 

    L1PICR bits 15:0 are the Invalidate Word Count Field.  L1PICR bit 31 is the IP bit which if set causes the entire L1P cache to be invalidated.

    The start address and word count do not need to be aligned by the programmer to a cache line (8 word) boundary;  this will be taken care of automatically by the cache controller;  the word count is automatically rounded up to make sure all L1P lines containing the memory between the starting byte address and length of word count 32-bit words is invalidated.

    Finally, the CPU needs to read the L1PICR and see tht the word count has reached zero before it branches into the region that it invalidated.